Blinky Verilog (DE1)

// AtomSoftTech (Jason Lopez) Blinky Test in Verilog for DE1
//
// PIN ASSIGNMENTS:
//   set_location_assignment PIN_L1 -to CLOCK_50
//   set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
//   set_location_assignment PIN_U22 -to CLOCK_2HZ
//   set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_2HZ
module SimpleUART(CLOCK_50,CLOCK_2HZ);

input CLOCK_50;
output  CLOCK_2HZ;

reg [31:0]  count;
reg [31:0]  cSpeed = 32'd25000000;
reg ClkOut = 1'b0;

always@(posedge CLOCK_50)

begin
    if(count == cSpeed)
        begin
            count = 0;
            ClkOut = ~ClkOut;
        end
    else
        count = count + 1;
end

assign CLOCK_2HZ = ClkOut;
endmodule