//
// HM2DPLL
//

typedef struct {
    hal_float_t *time1_ms;
    hal_float_t *time2_ms;
    hal_float_t *time3_ms;
    hal_float_t *time4_ms;
    hal_float_t *base_freq;
    hal_u32_t *phase_error;
    hal_u32_t *plimit;
    hal_u32_t *filter;
    hal_u32_t *ddssize;
    hal_u32_t *time_const;
    hal_u32_t *prescale;
} hm2_hm2dpll_pins_t ;

typedef struct {

    int num_instances ;
    hm2_hm2dpll_pins_t *pins ;

    u32 base_rate_addr;
    u32 base_rate_written;
    u32 phase_error_addr;
    u32 *phase_error_reg_read;
    u32 control_reg0_addr;
    u32 control_reg0_written;
    u32 control_reg1_addr;
    u32 control_reg1_written;
    u32 *control_reg1_read;
    u32 timer_12_addr;
    u32 timer_12_written;
    u32 timer_34_addr;
    u32 timer_34_written;
    u32 hm2_hm2dpll_sync_addr;
    u32 *hm2_hm2dpll_sync_reg;

} hm2_hm2dpll_t ;