Guest User

Untitled

a guest
Oct 26th, 2016
97
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 6.72 KB | None | 0 0
  1. diff --git a/arch/arm/boot/dts/armada-380-zyxel-nas326.dts b/arch/arm/boot/dts/armada-380-zyxel-nas326.dts
  2. new file mode 100644
  3. index 0000000..d94eaac
  4. --- /dev/null
  5. +++ b/arch/arm/boot/dts/armada-380-zyxel-nas326.dts
  6. @@ -0,0 +1,165 @@
  7. +/*
  8. + * Device Tree file for Marvell Armada 385 evaluation board
  9. + * (DB-88F6820)
  10. + *
  11. + * Copyright (C) 2013 Marvell
  12. + *
  13. + * Thomas Petazzoni <[email protected]>
  14. + *
  15. + * This file is licensed under the terms of the GNU General Public
  16. + * License version 2. This program is licensed "as is" without any
  17. + * warranty of any kind, whether express or implied.
  18. + */
  19. +
  20. +/dts-v1/;
  21. +#include "armada-380.dtsi"
  22. +
  23. +/ {
  24. + model = "Marvell Armada 380 STG-328";
  25. + compatible = "marvell,armada380", "marvell,armada38x";
  26. +
  27. + chosen {
  28. + bootargs = "console=ttyS0,115200";
  29. + };
  30. +
  31. + memory {
  32. + device_type = "memory";
  33. + reg = <0x00000000 0x10000000>; /* 256 MB */
  34. + };
  35. +
  36. + soc {
  37. + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  38. + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  39. + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 /* CESA0: PHYS=0xf1100000
  40. + size 64K */
  41. + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; /* CESA1: PHYS=0xf1110000
  42. + size 64K */
  43. +
  44. + internal-regs {
  45. + ethernet@70000 {
  46. + status = "okay";
  47. + phy-mode = "rgmii";
  48. + fixed-link {
  49. + speed = <1000>;
  50. + full-duplex;
  51. + };
  52. + };
  53. +
  54. + i2c0: i2c@11000 {
  55. + status = "okay";
  56. + clock-frequency = <100000>;
  57. + };
  58. +
  59. + i2c1: i2c@11100 {
  60. + status = "okay";
  61. + clock-frequency = <100000>;
  62. + };
  63. +
  64. + mdio {
  65. + status = "okay";
  66. + };
  67. +
  68. + sata@a8000 {
  69. + status = "okay";
  70. + };
  71. +
  72. +
  73. + sdhci@d8000 {
  74. + broken-cd;
  75. + wp-inverted;
  76. + bus-width = <8>;
  77. + status = "okay";
  78. + };
  79. +
  80. + serial@12000 {
  81. + status = "okay";
  82. + };
  83. +
  84. + spi0: spi@10600 {
  85. + status = "okay";
  86. +
  87. + spi-flash@0 {
  88. + #address-cells = <1>;
  89. + #size-cells = <1>;
  90. + compatible = "w25q32";
  91. + reg = <0>; /* Chip select 0 */
  92. + spi-max-frequency = <108000000>;
  93. + };
  94. + };
  95. +
  96. + /*
  97. + * 1GB Flash via NFC NAND controller
  98. + * by defeault disabled, because NFC
  99. + * shares same pins with SPI0 and
  100. + * requires SLM-1358 jumper
  101. + */
  102. + nfc: nand@d0000 {
  103. + #address-cells = <1>;
  104. + #size-cells = <1>;
  105. + clock-frequency = <200000000>;
  106. + status = "okay"; //BLUE_ADD...
  107. +
  108. + nfc,nfc-mode = "normal"; /* normal or ganged */
  109. + nfc,nfc-dma = <0>; /* 0 for no, 1 for dma */
  110. + nfc,nfc-width = <8>;
  111. + nfc,ecc-type = <1>; /* 4 bit */
  112. + nfc,num-cs = <1>;
  113. +
  114. + mtd0@00000000 {
  115. + label = "U-Boot";
  116. + reg = <0x00000000 0x00200000>; /* 2 MB */
  117. + };
  118. +
  119. + mtd1@00200000 {
  120. + label = "U-Boot env";
  121. + reg = <0x00200000 0x00200000>; /* 2 MB */
  122. + };
  123. +
  124. + mtd2@00400000 {
  125. + label = "Config";
  126. + reg = <0x00400000 0x00A00000>; /* 10 MB */
  127. + };
  128. +
  129. + mtd3@00600000 {
  130. + label = "Kernel-1";
  131. + reg = <0x00E00000 0x00F00000>; /* 15 MB */
  132. + };
  133. +
  134. + mtd4@01500000 {
  135. + label = "RootFS-1";
  136. + reg = <0x01D00000 0x06A00000>; /* 106 MB */
  137. + };
  138. +
  139. + mtd5@08300000 {
  140. + label = "Kernel-2";
  141. + reg = <0x08700000 0x00F00000>; /* 15 MB */
  142. + };
  143. +
  144. + mtd6@09200000 {
  145. + label = "RootFS-2";
  146. + reg = <0x09600000 0x06A00000>; /* 106 MB */
  147. + };
  148. + };
  149. +
  150. + crypto@9D000 {
  151. + status = "okay";
  152. + };
  153. + };
  154. +
  155. + pcie-controller {
  156. + status = "okay";
  157. + /*
  158. + * The two PCIe units are accessible through
  159. + * standard PCIe slots on the board.
  160. + */
  161. + pcie@1,0 {
  162. + /* Port 0, Lane 0 */
  163. + status = "okay";
  164. + };
  165. + pcie@2,0 {
  166. + /* Port 1, Lane 0 */
  167. + status = "okay";
  168. + };
  169. + };
  170. + };
  171. +};
Advertisement
Add Comment
Please, Sign In to add comment