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- library IEEE;
- use IEEE.std_logic_1164.all;
- entity alu1bit is
- port( i_X : in std_logic;
- i_Y : in std_logic;
- i_Less : in std_logic;
- i_Cin : in std_logic;
- i_Op : in std_logic_vector(3 downto 0);
- o_Res : out std_logic;
- o_Cout : out std_logic;
- o_Set : out std_logic);
- end alu1bit;
- architecture structure of alu1bit is
- component add_sub_wc is
- port( A : in std_logic;
- B : in std_logic;
- carry_in : in std_logic;
- nAdd_Sub : in std_logic;
- total : out std_logic;
- carry_out : out std_logic);
- end component;
- signal XYAnd, XYOr, XYXor, XYNand, XYNor, XYAdd, XYSub, XYSet, carry_add, carry_sub, YNot, XNot : std_logic;
- begin
- --Xmux and with Ymux
- XYAnd <= i_X AND i_Y;
- --Xmux or with Ymux
- XYOr <= i_X OR i_Y;
- --X Xor with Y
- XYXor <= i_X XOR i_Y;
- --X NAND with Y
- XYNand <= i_X NAND i_Y;
- --X NOR with Y
- XYNor <= i_X NOR i_Y;
- --Y Inverted
- YNot <= NOT i_Y;
- --X Inverted
- XNot <= NOT i_X;
- --Add X with Y
- addXY : add_sub_wc
- port map( A => i_X,
- B => i_Y,
- carry_in => i_Cin,
- nAdd_Sub => '0',
- total => XYAdd,
- carry_out => carry_add);
- --Subtract X with Y
- subXY : add_sub_wc
- port map( A => i_X,
- B => YNot,
- carry_in => i_Cin,
- nAdd_Sub => '0',
- total => XYsub,
- carry_out => carry_sub);
- --Select carryout value based on operation
- with i_OP select
- o_Cout <= carry_sub when "0011",
- carry_sub when "0111",
- carry_add when others;
- --Selecting which value we want to send to output
- with i_OP select
- o_Res <= XYAnd when "0000", --AND
- XYOr when "0001", --OR
- XYAdd when "0010", --ADD
- XYSub when "0011", --SUBTRACT
- XYNor when "0100", --NOR
- XYXor when "0101", --XOR
- XYNand when "0110", --NAND
- i_Less when "0111", --SET LESS THAN
- '0' when others;
- end structure;
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