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By: a guest on Nov 11th, 2012  |  syntax: None  |  size: 4.18 KB  |  views: 30  |  expires: Never
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  1. [mw@thanatos test]$ make sim_dtlb
  2. iverilog -o tb_lm32 tb_lm32.v lm32_include.v ../rtl/lm32_adder.v ../rtl/lm32_addsub.v ../rtl/lm32_cpu.v ../rtl/lm32_dcache.v ../rtl/lm32_debug.v ../rtl/lm32_decoder.v ../rtl/lm32_dp_ram.v ../rtl/lm32_icache.v ../rtl/lm32_instruction_unit.v ../rtl/lm32_interrupt.v ../rtl/lm32_jtag.v ../rtl/lm32_load_store_unit.v ../rtl/lm32_logic_op.v ../rtl/lm32_mc_arithmetic.v ../rtl/lm32_multiplier.v ../rtl/lm32_ram.v ../rtl/lm32_shifter.v ../rtl/lm32_itlb.v ../rtl/lm32_dtlb.v ../rtl/lm32_top.v
  3. VCD info: dumpfile tb_lm32.vcd opened for output.
  4. DTLB STATE MACHINE RESET
  5. ITLB STATE MACHINE RESET
  6. ITLB STATE MACHINE RESET
  7. DTLB STATE MACHINE RESET
  8. stack == 0x440070B4
  9. mapping 0x44002001->0x44001001 in slot 9 [0x44003d9c]
  10. stack == 0x440070B4
  11. mapping 0x44000001->0x44003001 in slot 8 [0x44003d90]
  12. stack == 0x440070B4
  13. mapping 0x44007001->0x44007001 in slot 7 [0x44003d84]
  14. stack == 0x440070B4
  15. mapping 0x44006001->0x44006001 in slot 6 [0x44003d78]
  16. stack == 0x440070C4
  17. addr == 0x44002004
  18. [MMU OFF] *(0x44002004) == 0x00010203
  19. [MMU ON] *(0x44002004) == 0x00010203
  20. [MMU OFF] *(0x44001004) == 0x469303AC
  21. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  22. Test n° 00 : PASS
  23. addr == 0x44002008
  24. [MMU OFF] *(0x44002008) == 0x01020304
  25. [MMU ON] *(0x44002008) == 0x01020304
  26. [MMU OFF] *(0x44001008) == 0x78014400
  27. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  28. Test n° 01 : PASS
  29. addr == 0x4400200C
  30. [MMU OFF] *(0x4400200C) == 0x02030405
  31. [MMU ON] *(0x4400200C) == 0x02030405
  32. [MMU OFF] *(0x4400100C) == 0x38213690
  33. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  34. Test n° 02 : PASS
  35. addr == 0x44002010
  36. [MMU OFF] *(0x44002010) == 0x03040506
  37. [MMU ON] *(0x44002010) == 0x03040506
  38. [MMU OFF] *(0x44001010) == 0xFBFFFC9E
  39. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  40. Test n° 03 : PASS
  41. addr == 0x44002014
  42. [MMU OFF] *(0x44002014) == 0x04050607
  43. [MMU ON] *(0x44002014) == 0x04050607
  44. [MMU OFF] *(0x44001014) == 0x35AD0001
  45. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  46. Test n° 04 : PASS
  47. addr == 0x44002018
  48. [MMU OFF] *(0x44002018) == 0x05060708
  49. [MMU ON] *(0x44002018) == 0x05060708
  50. [MMU OFF] *(0x44001018) == 0x78014400
  51. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  52. Test n° 05 : PASS
  53. addr == 0x4400201C
  54. [MMU OFF] *(0x4400201C) == 0x06070809
  55. [MMU ON] *(0x4400201C) == 0x06070809
  56. [MMU OFF] *(0x4400101C) == 0x78034400
  57. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  58. Test n° 06 : PASS
  59. addr == 0x44002020
  60. [MMU OFF] *(0x44002020) == 0x0708090A
  61. [MMU ON] *(0x44002020) == 0x0708090A
  62. [MMU OFF] *(0x44001020) == 0x382137F0
  63. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  64. Test n° 07 : PASS
  65. addr == 0x44002024
  66. [MMU OFF] *(0x44002024) == 0x08090A0B
  67. [MMU ON] *(0x44002024) == 0x08090A0B
  68. [MMU OFF] *(0x44001024) == 0x386337F4
  69. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  70. Test n° 08 : PASS
  71. addr == 0x44002028
  72. [MMU OFF] *(0x44002028) == 0x090A0B0C
  73. [MMU ON] *(0x44002028) == 0x090A0B0C
  74. [MMU OFF] *(0x44001028) == 0x28330000
  75. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  76. Test n° 09 : PASS
  77. addr == 0x4400202C
  78. [MMU OFF] *(0x4400202C) == 0x0A0B0C0D
  79. [MMU ON] *(0x4400202C) == 0x0A0B0C0D
  80. [MMU OFF] *(0x4400102C) == 0x28720000
  81. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  82. Test n° 10 : PASS
  83. addr == 0x44002030
  84. [MMU OFF] *(0x44002030) == 0x0B0C0D0E
  85. [MMU ON] *(0x44002030) == 0x0B0C0D0E
  86. [MMU OFF] *(0x44001030) == 0x91605800
  87. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  88. Test n° 11 : PASS
  89. addr == 0x44002034
  90. [MMU OFF] *(0x44002034) == 0x0C0D0E0F
  91. [MMU ON] *(0x44002034) == 0x0C0D0E0F
  92. [MMU OFF] *(0x44001034) == 0x396B0040
  93. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  94. Test n° 12 : PASS
  95. addr == 0x44002038
  96. [MMU OFF] *(0x44002038) == 0x0D0E0F10
  97. [MMU ON] *(0x44002038) == 0x0D0E0F10
  98. [MMU OFF] *(0x44001038) == 0xD16B0000
  99. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  100. Test n° 13 : PASS
  101. addr == 0x4400203C
  102. [MMU OFF] *(0x4400203C) == 0x0E0F1011
  103. [MMU ON] *(0x4400203C) == 0x0E0F1011
  104. [MMU OFF] *(0x4400103C) == 0x98000000
  105. [MMU ON] *(0x44000140) == 0x10E2D500 (283301120)
  106. Test n° 14 : PASS
  107. TOTAL : 15/15 successes | 0/15 failures
  108. ^C** VVP Stop(0) **
  109. ** Flushing output streams.
  110. ** Current simulation time is 3798545 ticks.
  111. > finish
  112. ** Continue **
  113.  
  114. [mw@thanatos test]$