----------------------------------------------------------------------------------
-- Company: Cal Poly SLO
-- Engineer: Louie Thiros
--
-- Create Date:    19:32:33 08/01/2014
-- Design Name:
-- Module Name:    Exp12 - Behavioral
-- Project Name:
-- Target Devices: Nexys3
-- Tool versions:
-- Description: A module that will dislpay the signed sum or difference of two
-- signed numbers as long as the result is valid.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Exp12 is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           ADD : in  STD_LOGIC;
           digit : out  STD_LOGIC_VECTOR (7 downto 0);
           anode : out  STD_LOGIC_VECTOR (3 downto 0);
           clk : in std_logic);
end Exp12;

architecture Behavioral of Exp12 is

    component RippleCarryAdder is
        Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           SUM : out  STD_LOGIC_VECTOR (3 downto 0);
           Cout : out  STD_LOGIC);
    end component;

    component signed_unsigned_dec is
        Port ( signed_4 : in  STD_LOGIC_VECTOR (3 downto 0);
           unsigned_4 : out  STD_LOGIC_VECTOR (3 downto 0));
    end component;

    component sseg_dec is
        Port (      ALU_VAL : in std_logic_vector(7 downto 0);
                        SIGN : in std_logic;
                        VALID : in std_logic;
                    CLK : in std_logic;
                DISP_EN : out std_logic_vector(3 downto 0);
               SEGMENTS : out std_logic_vector(7 downto 0));
    end component;

    component signed_inverter is
        Port( SIGNED_IN : in std_logic_vector(3 downto 0);
            SIGNED_OUT : out std_logic_vector (3 downto 0));
    end component;

    component signed_addition_validator is
        Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           SUM : in  STD_LOGIC;
           VALID : out  STD_LOGIC);
    end component;

    signal SELECTED_B, INVERTED_B, SUM, ABS_OF_SUM : std_logic_vector (3 downto 0);
    signal VALID : std_logic;

begin

    si0 : signed_inverter port map( SIGNED_IN => B,
        SIGNED_OUT => INVERTED_B);

    -- Mult the input by -1 when add isn't selected
    with ADD select
        SELECTED_B <= B when '1',
        INVERTED_B when others;

    rca0 : RippleCarryAdder port map( A => A,
        B => SELECTED_B,
        SUM => SUM);

    -- finds abs value of the added numbers for display
    sud0 : signed_unsigned_dec port map(signed_4 => SUM,
        unsigned_4 => ABS_OF_SUM);

    sav0 : signed_addition_validator port map(A => A(3),
        B => B(3),
        SUM => SUM(3),
        VALID => VALID);

    sd0 : sseg_dec port map(ALU_VAL => "0000" & ABS_OF_SUM,
        SIGN => SUM(3),
        VALID => '1',
        CLK => clk,
        DISP_EN => anode,
        SEGMENTS => digit);
end Behavioral;