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stm32f4x7_eth_v2.c

teplofizik
Jun 8th, 2016
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  1. // Уменьшенные в ~16 раз тайминги
  2. #define PHY_READ_TO ((uint32_t)0x0004FFF)
  3. #define PHY_WRITE_TO ((uint32_t)0x0004FFF)
  4.  
  5. // проверка состояния регистров РНУ
  6. void ETH_Test(uint16_t PHYAddress, uint32_t * Dest)
  7. {
  8. uint32_t Temp[32];
  9. int i;
  10.  
  11. for(i = 0; i < 32; i++)
  12. {
  13. Temp[i] = ETH_ReadPHYRegister(PHYAddress, i);
  14. }
  15.  
  16. if(Dest) memcpy(Dest, &Temp[0], sizeof(Temp));
  17. }
  18.  
  19. uint32_t ETH_RestartAutoneg(uint16_t PHYAddress)
  20. {
  21. if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation | PHY_Restart_AutoNegotiation))
  22. return ETH_ERROR;
  23. else
  24. return ETH_SUCCESS;
  25. }
  26.  
  27. uint32_t ETH_AutonegotiationCompleted(ETH_InitTypeDef * ETH_InitStruct, uint16_t PHYAddress)
  28. {
  29. uint32_t tmpreg = 0;
  30. /* Read the result of the auto-negotiation */
  31. {
  32. uint32_t RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_ANLPA);
  33. #if (ALLOW_100MBIT == 1)
  34. if(RegValue & (1 << 8))
  35. {
  36. // 10 full
  37. ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
  38. ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
  39. }
  40. else if(RegValue & (1 << 7))
  41. {
  42. // 10 full
  43. ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
  44. ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
  45. }
  46. else
  47. #endif
  48. if(RegValue & (1 << 6))
  49. {
  50. // 10 full
  51. ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
  52. ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
  53. }
  54. else
  55. {
  56. // Only 10 half
  57. ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
  58. ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
  59. }
  60. }
  61.  
  62. // ETH_WritePHYRegister(PHYAddress, 31, 0); // Disable 4B5B
  63.  
  64. /*------------------------ ETHERNET MACCR Configuration --------------------*/
  65. /* Get the ETHERNET MACCR value */
  66. tmpreg = ETH->MACCR;
  67. /* Clear WD, PCE, PS, TE and RE bits */
  68. tmpreg &= MACCR_CLEAR_MASK;
  69. /* Set the WD bit according to ETH_Watchdog value */
  70. /* Set the JD: bit according to ETH_Jabber value */
  71. /* Set the IFG bit according to ETH_InterFrameGap value */
  72. /* Set the DCRS bit according to ETH_CarrierSense value */
  73. /* Set the FES bit according to ETH_Speed value */
  74. /* Set the DO bit according to ETH_ReceiveOwn value */
  75. /* Set the LM bit according to ETH_LoopbackMode value */
  76. /* Set the DM bit according to ETH_Mode value */
  77. /* Set the IPCO bit according to ETH_ChecksumOffload value */
  78. /* Set the DR bit according to ETH_RetryTransmission value */
  79. /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
  80. /* Set the BL bit according to ETH_BackOffLimit value */
  81. /* Set the DC bit according to ETH_DeferralCheck value */
  82. tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
  83. ETH_InitStruct->ETH_Jabber |
  84. ETH_InitStruct->ETH_InterFrameGap |
  85. ETH_InitStruct->ETH_CarrierSense |
  86. ETH_InitStruct->ETH_Speed |
  87. ETH_InitStruct->ETH_ReceiveOwn |
  88. ETH_InitStruct->ETH_LoopbackMode |
  89. ETH_InitStruct->ETH_Mode |
  90. ETH_InitStruct->ETH_ChecksumOffload |
  91. ETH_InitStruct->ETH_RetryTransmission |
  92. ETH_InitStruct->ETH_AutomaticPadCRCStrip |
  93. ETH_InitStruct->ETH_BackOffLimit |
  94. ETH_InitStruct->ETH_DeferralCheck);
  95. /* Write to ETHERNET MACCR */
  96. ETH->MACCR = (uint32_t)tmpreg;
  97.  
  98. /*----------------------- ETHERNET MACFFR Configuration --------------------*/
  99. /* Set the RA bit according to ETH_ReceiveAll value */
  100. /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
  101. /* Set the PCF bit according to ETH_PassControlFrames value */
  102. /* Set the DBF bit according to ETH_BroadcastFramesReception value */
  103. /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
  104. /* Set the PR bit according to ETH_PromiscuousMode value */
  105. /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
  106. /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
  107. /* Write to ETHERNET MACFFR */
  108. ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
  109. ETH_InitStruct->ETH_SourceAddrFilter |
  110. ETH_InitStruct->ETH_PassControlFrames |
  111. ETH_InitStruct->ETH_BroadcastFramesReception |
  112. ETH_InitStruct->ETH_DestinationAddrFilter |
  113. ETH_InitStruct->ETH_PromiscuousMode |
  114. ETH_InitStruct->ETH_MulticastFramesFilter |
  115. ETH_InitStruct->ETH_UnicastFramesFilter);
  116. /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
  117. /* Write to ETHERNET MACHTHR */
  118. ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
  119. /* Write to ETHERNET MACHTLR */
  120. ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
  121. /*----------------------- ETHERNET MACFCR Configuration --------------------*/
  122. /* Get the ETHERNET MACFCR value */
  123. tmpreg = ETH->MACFCR;
  124. /* Clear xx bits */
  125. tmpreg &= MACFCR_CLEAR_MASK;
  126.  
  127. /* Set the PT bit according to ETH_PauseTime value */
  128. /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
  129. /* Set the PLT bit according to ETH_PauseLowThreshold value */
  130. /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
  131. /* Set the RFE bit according to ETH_ReceiveFlowControl value */
  132. /* Set the TFE bit according to ETH_TransmitFlowControl value */
  133. tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
  134. ETH_InitStruct->ETH_ZeroQuantaPause |
  135. ETH_InitStruct->ETH_PauseLowThreshold |
  136. ETH_InitStruct->ETH_UnicastPauseFrameDetect |
  137. ETH_InitStruct->ETH_ReceiveFlowControl |
  138. ETH_InitStruct->ETH_TransmitFlowControl);
  139. /* Write to ETHERNET MACFCR */
  140. ETH->MACFCR = (uint32_t)tmpreg;
  141. /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
  142. /* Set the ETV bit according to ETH_VLANTagComparison value */
  143. /* Set the VL bit according to ETH_VLANTagIdentifier value */
  144. ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
  145. ETH_InitStruct->ETH_VLANTagIdentifier);
  146.  
  147. /*-------------------------------- DMA Config ------------------------------*/
  148. /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
  149. /* Get the ETHERNET DMAOMR value */
  150. tmpreg = ETH->DMAOMR;
  151. /* Clear xx bits */
  152. tmpreg &= DMAOMR_CLEAR_MASK;
  153.  
  154. /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
  155. /* Set the RSF bit according to ETH_ReceiveStoreForward value */
  156. /* Set the DFF bit according to ETH_FlushReceivedFrame value */
  157. /* Set the TSF bit according to ETH_TransmitStoreForward value */
  158. /* Set the TTC bit according to ETH_TransmitThresholdControl value */
  159. /* Set the FEF bit according to ETH_ForwardErrorFrames value */
  160. /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
  161. /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
  162. /* Set the OSF bit according to ETH_SecondFrameOperate value */
  163. tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
  164. ETH_InitStruct->ETH_ReceiveStoreForward |
  165. ETH_InitStruct->ETH_FlushReceivedFrame |
  166. ETH_InitStruct->ETH_TransmitStoreForward |
  167. ETH_InitStruct->ETH_TransmitThresholdControl |
  168. ETH_InitStruct->ETH_ForwardErrorFrames |
  169. ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
  170. ETH_InitStruct->ETH_ReceiveThresholdControl |
  171. ETH_InitStruct->ETH_SecondFrameOperate);
  172. /* Write to ETHERNET DMAOMR */
  173. ETH->DMAOMR = (uint32_t)tmpreg;
  174.  
  175. /*----------------------- ETHERNET DMABMR Configuration --------------------*/
  176. /* Set the AAL bit according to ETH_AddressAlignedBeats value */
  177. /* Set the FB bit according to ETH_FixedBurst value */
  178. /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
  179. /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
  180. /* Set the DSL bit according to ETH_DesciptorSkipLength value */
  181. /* Set the PR and DA bits according to ETH_DMAArbitration value */
  182. ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
  183. ETH_InitStruct->ETH_FixedBurst |
  184. ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
  185. ETH_InitStruct->ETH_TxDMABurstLength |
  186. (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
  187. ETH_InitStruct->ETH_DMAArbitration |
  188. ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
  189.  
  190. #ifdef USE_ENHANCED_DMA_DESCRIPTORS
  191. /* Enable the Enhanced DMA descriptors */
  192. ETH->DMABMR |= ETH_DMABMR_EDE;
  193. #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
  194.  
  195. return ETH_SUCCESS;
  196. }
  197.  
  198.  
  199. /**
  200. * @brief Initializes the ETHERNET peripheral according to the specified
  201. * parameters in the ETH_InitStruct .
  202. * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains
  203. * the configuration information for the specified ETHERNET peripheral.
  204. * @param PHYAddress: external PHY address
  205. * @retval ETH_ERROR: Ethernet initialization failed
  206. * ETH_SUCCESS: Ethernet successfully initialized
  207. */
  208. uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
  209. {
  210. uint32_t RegValue = 0, tmpreg = 0;
  211. __IO uint32_t i = 0;
  212. RCC_ClocksTypeDef rcc_clocks;
  213. uint32_t hclk = 60000000;
  214. __IO uint32_t timeout = 0;
  215. /* Check the parameters */
  216. /* MAC --------------------------*/
  217. assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
  218. assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
  219. assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
  220. assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
  221. assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
  222. assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
  223. assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
  224. assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
  225. assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
  226. assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
  227. assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
  228. assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
  229. assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
  230. assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
  231. assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
  232. assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
  233. assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
  234. assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
  235. assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
  236. assert_param(IS_ETH_PROMISCIOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
  237. assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
  238. assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
  239. assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
  240. assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
  241. assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
  242. assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
  243. assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
  244. assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
  245. assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
  246. assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
  247. /* DMA --------------------------*/
  248. assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
  249. assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
  250. assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
  251. assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
  252. assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
  253. assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
  254. assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
  255. assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
  256. assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
  257. assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
  258. assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
  259. assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
  260. assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
  261. assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
  262. assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
  263. /*-------------------------------- MAC Config ------------------------------*/
  264. /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
  265. /* Get the ETHERNET MACMIIAR value */
  266. tmpreg = ETH->MACMIIAR;
  267. /* Clear CSR Clock Range CR[2:0] bits */
  268. tmpreg &= MACMIIAR_CR_MASK;
  269. /* Get hclk frequency value */
  270. RCC_GetClocksFreq(&rcc_clocks);
  271. hclk = rcc_clocks.HCLK_Frequency;
  272.  
  273. /* Set CR bits depending on hclk value */
  274. if((hclk >= 20000000)&&(hclk < 35000000))
  275. {
  276. /* CSR Clock Range between 20-35 MHz */
  277. tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
  278. }
  279. else if((hclk >= 35000000)&&(hclk < 60000000))
  280. {
  281. /* CSR Clock Range between 35-60 MHz */
  282. tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
  283. }
  284. else if((hclk >= 60000000)&&(hclk < 100000000))
  285. {
  286. /* CSR Clock Range between 60-100 MHz */
  287. tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
  288. }
  289. else if((hclk >= 100000000)&&(hclk < 150000000))
  290. {
  291. /* CSR Clock Range between 100-150 MHz */
  292. tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
  293. }
  294. else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
  295. {
  296. /* CSR Clock Range between 150-168 MHz */
  297. tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
  298. }
  299.  
  300. /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
  301. ETH->MACMIIAR = (uint32_t)tmpreg;
  302. /*-------------------- PHY initialization and configuration ----------------*/
  303.  
  304. /* Put the PHY in reset mode */
  305. // if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
  306. // {
  307. /* Return ERROR in case of write timeout */
  308. // return ETH_ERROR;
  309. // }
  310.  
  311. /* Delay to assure PHY reset */
  312. _eth_delay_(PHY_RESET_DELAY);
  313.  
  314.  
  315. TestPHY();
  316. if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
  317. {
  318. #if (ALLOW_100MBIT == 1)
  319. if(!(ETH_WritePHYRegister(PHYAddress, PHY_ANAR, 0x01E1))) // Only 100 Mbit
  320. #else
  321. if(!(ETH_WritePHYRegister(PHYAddress, PHY_ANAR, 0x0061))) // Only 10 Mbit
  322. #endif
  323. {
  324. /* Return ERROR in case of write timeout */
  325. return ETH_ERROR;
  326. }
  327. /*
  328. // We wait for linked status...
  329. do
  330. {
  331. timeout++;
  332. wdt_Reset();
  333. } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
  334.  
  335. // Return ERROR in case of timeout
  336. if(timeout == PHY_READ_TO)
  337. {
  338. return ETH_ERROR;
  339. }
  340. */
  341.  
  342. // Reset Timeout counter
  343. timeout = 0;
  344. // Enable Auto-Negotiation
  345. if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation | PHY_Restart_AutoNegotiation)))
  346. {
  347. // Return ERROR in case of write timeout
  348. return ETH_ERROR;
  349. }
  350.  
  351. /* Reset Timeout counter */
  352. timeout = 0;
  353. do
  354. {
  355. timeout++;
  356. wdt_Reset();
  357. delay(2);
  358. } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < PHY_READ_TO));
  359.  
  360. /* Return ERROR in case of timeout */
  361. if(timeout == PHY_READ_TO)
  362. {
  363. return ETH_ERROR;
  364. }
  365.  
  366. /* Reset Timeout counter */
  367. timeout = 0;
  368.  
  369. TestPHY();
  370. {
  371. RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_ANLPA);
  372. #if (ALLOW_100MBIT == 1)
  373. if(RegValue & (1 << 8))
  374. {
  375. // 10 full
  376. ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
  377. ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
  378. }
  379. else if(RegValue & (1 << 7))
  380. {
  381. // 10 full
  382. ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
  383. ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
  384. }
  385. else
  386. #endif
  387. if(RegValue & (1 << 6))
  388. {
  389. // 10 full
  390. ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
  391. ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
  392. }
  393. else
  394. {
  395. // Only 10 half
  396. ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
  397. ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
  398. }
  399. }
  400. }
  401. else
  402. {
  403. if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
  404. (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
  405. {
  406. /* Return ERROR in case of write timeout */
  407. return ETH_ERROR;
  408. }
  409.  
  410. /* Delay to assure PHY configuration */
  411. _eth_delay_(PHY_CONFIG_DELAY);
  412.  
  413. }
  414.  
  415. // ETH_WritePHYRegister(PHYAddress, 31, 0); // Disable 4B5B
  416.  
  417. /*------------------------ ETHERNET MACCR Configuration --------------------*/
  418. /* Get the ETHERNET MACCR value */
  419. tmpreg = ETH->MACCR;
  420. /* Clear WD, PCE, PS, TE and RE bits */
  421. tmpreg &= MACCR_CLEAR_MASK;
  422. /* Set the WD bit according to ETH_Watchdog value */
  423. /* Set the JD: bit according to ETH_Jabber value */
  424. /* Set the IFG bit according to ETH_InterFrameGap value */
  425. /* Set the DCRS bit according to ETH_CarrierSense value */
  426. /* Set the FES bit according to ETH_Speed value */
  427. /* Set the DO bit according to ETH_ReceiveOwn value */
  428. /* Set the LM bit according to ETH_LoopbackMode value */
  429. /* Set the DM bit according to ETH_Mode value */
  430. /* Set the IPCO bit according to ETH_ChecksumOffload value */
  431. /* Set the DR bit according to ETH_RetryTransmission value */
  432. /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
  433. /* Set the BL bit according to ETH_BackOffLimit value */
  434. /* Set the DC bit according to ETH_DeferralCheck value */
  435. tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
  436. ETH_InitStruct->ETH_Jabber |
  437. ETH_InitStruct->ETH_InterFrameGap |
  438. ETH_InitStruct->ETH_CarrierSense |
  439. ETH_InitStruct->ETH_Speed |
  440. ETH_InitStruct->ETH_ReceiveOwn |
  441. ETH_InitStruct->ETH_LoopbackMode |
  442. ETH_InitStruct->ETH_Mode |
  443. ETH_InitStruct->ETH_ChecksumOffload |
  444. ETH_InitStruct->ETH_RetryTransmission |
  445. ETH_InitStruct->ETH_AutomaticPadCRCStrip |
  446. ETH_InitStruct->ETH_BackOffLimit |
  447. ETH_InitStruct->ETH_DeferralCheck);
  448. /* Write to ETHERNET MACCR */
  449. ETH->MACCR = (uint32_t)tmpreg;
  450.  
  451. /*----------------------- ETHERNET MACFFR Configuration --------------------*/
  452. /* Set the RA bit according to ETH_ReceiveAll value */
  453. /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
  454. /* Set the PCF bit according to ETH_PassControlFrames value */
  455. /* Set the DBF bit according to ETH_BroadcastFramesReception value */
  456. /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
  457. /* Set the PR bit according to ETH_PromiscuousMode value */
  458. /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
  459. /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
  460. /* Write to ETHERNET MACFFR */
  461. ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
  462. ETH_InitStruct->ETH_SourceAddrFilter |
  463. ETH_InitStruct->ETH_PassControlFrames |
  464. ETH_InitStruct->ETH_BroadcastFramesReception |
  465. ETH_InitStruct->ETH_DestinationAddrFilter |
  466. ETH_InitStruct->ETH_PromiscuousMode |
  467. ETH_InitStruct->ETH_MulticastFramesFilter |
  468. ETH_InitStruct->ETH_UnicastFramesFilter);
  469. /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
  470. /* Write to ETHERNET MACHTHR */
  471. ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
  472. /* Write to ETHERNET MACHTLR */
  473. ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
  474. /*----------------------- ETHERNET MACFCR Configuration --------------------*/
  475. /* Get the ETHERNET MACFCR value */
  476. tmpreg = ETH->MACFCR;
  477. /* Clear xx bits */
  478. tmpreg &= MACFCR_CLEAR_MASK;
  479.  
  480. /* Set the PT bit according to ETH_PauseTime value */
  481. /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
  482. /* Set the PLT bit according to ETH_PauseLowThreshold value */
  483. /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
  484. /* Set the RFE bit according to ETH_ReceiveFlowControl value */
  485. /* Set the TFE bit according to ETH_TransmitFlowControl value */
  486. tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
  487. ETH_InitStruct->ETH_ZeroQuantaPause |
  488. ETH_InitStruct->ETH_PauseLowThreshold |
  489. ETH_InitStruct->ETH_UnicastPauseFrameDetect |
  490. ETH_InitStruct->ETH_ReceiveFlowControl |
  491. ETH_InitStruct->ETH_TransmitFlowControl);
  492. /* Write to ETHERNET MACFCR */
  493. ETH->MACFCR = (uint32_t)tmpreg;
  494. /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
  495. /* Set the ETV bit according to ETH_VLANTagComparison value */
  496. /* Set the VL bit according to ETH_VLANTagIdentifier value */
  497. ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
  498. ETH_InitStruct->ETH_VLANTagIdentifier);
  499.  
  500. /*-------------------------------- DMA Config ------------------------------*/
  501. /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
  502. /* Get the ETHERNET DMAOMR value */
  503. tmpreg = ETH->DMAOMR;
  504. /* Clear xx bits */
  505. tmpreg &= DMAOMR_CLEAR_MASK;
  506.  
  507. /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
  508. /* Set the RSF bit according to ETH_ReceiveStoreForward value */
  509. /* Set the DFF bit according to ETH_FlushReceivedFrame value */
  510. /* Set the TSF bit according to ETH_TransmitStoreForward value */
  511. /* Set the TTC bit according to ETH_TransmitThresholdControl value */
  512. /* Set the FEF bit according to ETH_ForwardErrorFrames value */
  513. /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
  514. /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
  515. /* Set the OSF bit according to ETH_SecondFrameOperate value */
  516. tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
  517. ETH_InitStruct->ETH_ReceiveStoreForward |
  518. ETH_InitStruct->ETH_FlushReceivedFrame |
  519. ETH_InitStruct->ETH_TransmitStoreForward |
  520. ETH_InitStruct->ETH_TransmitThresholdControl |
  521. ETH_InitStruct->ETH_ForwardErrorFrames |
  522. ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
  523. ETH_InitStruct->ETH_ReceiveThresholdControl |
  524. ETH_InitStruct->ETH_SecondFrameOperate);
  525. /* Write to ETHERNET DMAOMR */
  526. ETH->DMAOMR = (uint32_t)tmpreg;
  527.  
  528. /*----------------------- ETHERNET DMABMR Configuration --------------------*/
  529. /* Set the AAL bit according to ETH_AddressAlignedBeats value */
  530. /* Set the FB bit according to ETH_FixedBurst value */
  531. /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
  532. /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
  533. /* Set the DSL bit according to ETH_DesciptorSkipLength value */
  534. /* Set the PR and DA bits according to ETH_DMAArbitration value */
  535. ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
  536. ETH_InitStruct->ETH_FixedBurst |
  537. ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
  538. ETH_InitStruct->ETH_TxDMABurstLength |
  539. (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
  540. ETH_InitStruct->ETH_DMAArbitration |
  541. ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
  542.  
  543. #ifdef USE_ENHANCED_DMA_DESCRIPTORS
  544. /* Enable the Enhanced DMA descriptors */
  545. ETH->DMABMR |= ETH_DMABMR_EDE;
  546. #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
  547.  
  548. TestPHY();
  549. {
  550. // bool Res = ETH_HasLink(PHYAddress);
  551. // if(!Res)
  552. // return ETH_ERROR;
  553.  
  554. //bool Res = ETH_HasSymbolError(PHYAddress);
  555. //if(Res)
  556. // return ETH_ERROR;
  557.  
  558. //if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
  559. //{
  560. //Res = ETH_HasNextPageAb(PHYAddress);
  561. //if(!Res)
  562. // return ETH_ERROR;
  563. //}
  564.  
  565. }
  566.  
  567. /* Return Ethernet configuration success */
  568. return ETH_SUCCESS;
  569. }
  570.  
  571. bool ETH_HasLink(uint16_t PHYAddress)
  572. {
  573. uint32_t PHY = ETH_ReadPHYRegister(PHYAddress, PHY_BSR);
  574. return ((PHY & PHY_Linked_Status) != 0);
  575. }
  576.  
  577. bool ETH_AutoNegCompleted(uint16_t PHYAddress)
  578. {
  579. return (ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) != 0;
  580. }
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