library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity three_input_gate is
	port (
	    CK, S, P : in  std_logic;
		 Q : out std_logic
	);
end entity;

architecture IMP of three_input_gate is
begin
	Q <= (not P) or (CK and S);
end IMP;