Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
- index dec6f8d6..0f2cc0a 100644
- --- a/drivers/clk/rockchip/clk.c
- +++ b/drivers/clk/rockchip/clk.c
- @@ -41,6 +41,7 @@
- static struct clk *rockchip_clk_register_branch(const char *name,
- const char **parent_names, u8 num_parents, void __iomem *base,
- int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
- + struct clk_ops *muxops,
- u8 div_shift, u8 div_width, u8 div_flags,
- struct clk_div_table *div_table, int gate_offset,
- u8 gate_shift, u8 gate_flags, unsigned long flags,
- @@ -63,8 +64,13 @@ static struct clk *rockchip_clk_register_branch(const char *name,
- mux->mask = BIT(mux_width) - 1;
- mux->flags = mux_flags;
- mux->lock = lock;
- - mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
- - : &clk_mux_ops;
- +
- + if (muxops)
- + mux_ops = muxops;
- + else if (mux_flags & CLK_MUX_READ_ONLY)
- + mux_ops = &clk_mux_ro_ops;
- + else
- + mux_ops = &clk_mux_ops;
- }
- if (gate_offset >= 0) {
- @@ -265,6 +271,7 @@ void __init rockchip_clk_register_branches(
- list->parent_names, list->num_parents,
- reg_base, list->muxdiv_offset, list->mux_shift,
- list->mux_width, list->mux_flags,
- + list->mux_ops,
- list->div_shift, list->div_width,
- list->div_flags, list->div_table,
- list->gate_offset, list->gate_shift,
- diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
- index 6baf665..2998967 100644
- --- a/drivers/clk/rockchip/clk.h
- +++ b/drivers/clk/rockchip/clk.h
- @@ -182,6 +182,7 @@ struct rockchip_clk_branch {
- u8 mux_shift;
- u8 mux_width;
- u8 mux_flags;
- + struct clk_ops *mux_ops;
- u8 div_shift;
- u8 div_width;
- u8 div_flags;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement