module f_bit(M, R, MULT, A, S, P);

    input [3:0] M;
    input [3:0] R;

    output reg [7:0] MULT;
    reg l;

    output reg [8:0] A, S, P;


    always @*
    begin

        A = {M, 4'b0, 1'b0};
        S = {-M, 4'b0, 1'b0};
        P = {4'b0, R, 1'b0};

        repeat(4)
        begin

            case (P[1:0])
                2'b01: P = P + A;
                2'b10: P = P + S;
                default : ;
            endcase

            P = P >>> 1'b1;

        end

        {MULT, l} = P;

    end



endmodule