library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity CodigoRedundanciaCiclica is
     Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           serialin : in  STD_LOGIC;
           CRC : out  STD_LOGIC_VECTOR (11 downto 0));
end CodigoRedundanciaCiclica;

architecture Behavioral of CodigoRedundanciaCiclica is
signal salidaP   : STD_LOGIC_VECTOR (4 downto 0);
signal salidaB   : STD_LOGIC_VECTOR (11 downto 0);

component puertaXOR is
    Port ( inA  : in    STD_LOGIC;
          inB   : in    STD_LOGIC;
          outC  : out   STD_LOGIC);
end component;

component biestable is
    Port ( rst  : in    STD_LOGIC;
          clk   : in    STD_LOGIC;
          i : in    STD_LOGIC;
          o : inout STD_LOGIC);
end component;

begin
    BIS0 : biestable port map(rst, clk, salidaP(4), salidaB(0));
    BIS1 : biestable port map(rst, clk, salidaP(0), salidaB(1));
    BIS2 : biestable port map(rst, clk, salidaP(1), salidaB(2));
    BIS3 : biestable port map(rst, clk, salidaP(2), salidaB(3));
    BIS4 : biestable port map(rst, clk, salidaB(3), salidaB(4));
    BIS5 : biestable port map(rst, clk, salidaB(4), salidaB(5));
    BIS6 : biestable port map(rst, clk, salidaB(5), salidaB(6));
    BIS7 : biestable port map(rst, clk, salidaB(6), salidaB(7));
    BIS8 : biestable port map(rst, clk, salidaB(7), salidaB(8));
    BIS9 : biestable port map(rst, clk, salidaB(8), salidaB(9));
    BIS10 : biestable port map(rst, clk, salidaB(9), salidaB(10));
    BIS11 : biestable port map(rst, clk, salidaP(3), salidaB(11));

    PXOR0 : puertaXOR port map(salidaP(4), salidaB(0), salidaP(0));
    PXOR1 : puertaXOR port map(salidaP(4), salidaB(1), salidaP(1));
    PXOR2 : puertaXOR port map(salidaP(4), salidaB(2), salidaP(2));
    PXOR3 : puertaXOR port map(salidaP(4), salidaB(10), salidaP(3));
    PXOR4 : puertaXOR port map(salidaB(11), serialin, salidaP(4));

    CRC(0) <= salidaB(11);
    CRC(1) <= salidaB(10);
    CRC(2) <= salidaB(9);
    CRC(3) <= salidaB(8);
    CRC(4) <= salidaB(7);
    CRC(5) <= salidaB(6);
    CRC(6) <= salidaB(5);
    CRC(7) <= salidaB(4);
    CRC(8) <= salidaB(3);
    CRC(9) <= salidaB(2);
    CRC(10) <= salidaB(1);
    CRC(11) <= salidaB(0);
end Behavioral;