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  1. =========================================================================
  2.  
  3. =========================================================================
  4. * Partition Report *
  5. =========================================================================
  6.  
  7. Partition Implementation Status
  8. -------------------------------
  9.  
  10. No Partitions were found in this design.
  11.  
  12. -------------------------------
  13.  
  14. =========================================================================
  15. * Design Summary *
  16. =========================================================================
  17.  
  18. Clock Information:
  19. ------------------
  20. -----------------------------------+--------------------------------+-------+
  21. Clock Signal | Clock buffer(FF name) | Load |
  22. -----------------------------------+--------------------------------+-------+
  23. clkgen0/pll0/CLKOUT1 | BUFG | 5694 |
  24. sys_clk_pad_i | DCM_SP:CLKFX180+PLL_ADV:CLKOUT3| 237 |
  25. eth0_rx_clk | IBUF | 297 |
  26. eth0_tx_clk | IBUF | 231 |
  27. sys_clk_pad_i | DCM_SP:CLKDV | 69 |
  28. dvi_gen0/PLL_OSERDES/CLKOUT2 | BUFG | 55 |
  29. dvi_gen0/PLL_OSERDES/CLKOUT1 | BUFG | 315 |
  30. tck_pad_i | BUFGP | 558 |
  31. ac97_bit_clk_pad_i | IBUF | 9 |
  32. sys_clk_pad_i | DCM_SP:CLKFX180+PLL_ADV:CLKOUT2| 26 |
  33. -----------------------------------+--------------------------------+-------+
  34.  
  35. Asynchronous Control Signals Information:
  36. ----------------------------------------
  37. No asynchronous control signals found in this design
  38.  
  39. Timing Summary:
  40. ---------------
  41. Speed Grade: -2
  42.  
  43. Minimum period: 15.384ns (Maximum Frequency: 65.001MHz)
  44. Minimum input arrival time before clock: 10.434ns
  45. Maximum output required time after clock: 17.099ns
  46. Maximum combinational path delay: 4.654ns
  47.  
  48. =========================================================================
  49.  
  50. Process "Synthesize - XST" completed successfully
  51.  
  52. Started : "Translate".
  53. Running ngdbuild...
  54. Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /run/media/hesham/2cdb13e0-83ac-4ebd-9ead-be52de50707c/home/hesham/OpenRISC/fusesoc/build/atlys/src/atlys/data/atlys.ucf -p xc6slx45-csg324-2 orpsoc_top.ngc orpsoc_top.ngd
  55.  
  56. Command Line: /opt/Xilinx/14.6/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
  57. ise -dd _ngo -nt timestamp -uc
  58. /run/media/hesham/2cdb13e0-83ac-4ebd-9ead-be52de50707c/home/hesham/OpenRISC/fuse
  59. soc/build/atlys/src/atlys/data/atlys.ucf -p xc6slx45-csg324-2 orpsoc_top.ngc
  60. orpsoc_top.ngd
  61.  
  62. Reading NGO file
  63. "/run/media/hesham/2cdb13e0-83ac-4ebd-9ead-be52de50707c/home/hesham/OpenRISC/fus
  64. esoc/build/atlys/bld-ise/orpsoc_top.ngc" ...
  65. Gathering constraint information from source properties...
  66. Done.
  67.  
  68. Annotating constraints to design from ucf file
  69. "/run/media/hesham/2cdb13e0-83ac-4ebd-9ead-be52de50707c/home/hesham/OpenRISC/fus
  70. esoc/build/atlys/src/atlys/data/atlys.ucf" ...
  71. WARNING:NgdBuild - The value of SIM_DEVICE on instance
  72. 'xilinx_ddr2_0/xilinx_ddr2_if0/ddr2_mig/memc3_infrastructure_inst/u_pll_adv'
  73. of type PLL_ADV has been changed from 'VIRTEX5' to 'SPARTAN6' to correct
  74. post-ngdbuild and timing simulation for this primitive. In order for
  75. functional simulation to be correct, the value of SIM_DEVICE should be
  76. changed in this same manner in the source netlist or constraint file.
  77. Resolving constraint associations...
  78. Checking Constraint Associations...
  79.  
  80.  
  81.  
  82.  
  83.  
  84.  
  85.  
  86.  
  87.  
  88.  
  89.  
  90.  
  91.  
  92.  
  93.  
  94.  
  95. Done...
  96.  
  97. WARNING:NgdBuild:1440 - User specified non-default attribute value (3.75) was
  98. detected for the CLKIN1_PERIOD attribute on PLL
  99. "xilinx_ddr2_0/xilinx_ddr2_if0/ddr2_mig/memc3_infrastructure_inst/u_pll_adv".
  100. This does not match the PERIOD constraint value (266.666667 MHz.). The
  101. uncertainty calculation will use the PERIOD constraint value. This could
  102. result in incorrect uncertainty calculated for PLL output clocks.
  103. WARNING:NgdBuild:1440 - User specified non-default attribute value (13) was
  104. detected for the CLKIN1_PERIOD attribute on PLL "PLL_ADV". This does not
  105. match the PERIOD constraint value (73.8095238 MHz.). The uncertainty
  106. calculation will use the PERIOD constraint value. This could result in
  107. incorrect uncertainty calculated for PLL output clocks.
  108. Checking expanded design ...
  109. WARNING:NgdBuild:452 - logical net 'N3697' has no driver
  110. WARNING:NgdBuild:452 - logical net 'N3699' has no driver
  111.  
  112. Partition Implementation Status
  113. -------------------------------
  114.  
  115. No Partitions were found in this design.
  116.  
  117. -------------------------------
  118.  
  119. NGDBUILD Design Results Summary:
  120. Number of errors: 0
  121. Number of warnings: 5
  122.  
  123. Writing NGD file "orpsoc_top.ngd" ...
  124. Total REAL time to NGDBUILD completion: 15 sec
  125. Total CPU time to NGDBUILD completion: 15 sec
  126.  
  127. Writing NGDBUILD log file "orpsoc_top.bld"...
  128.  
  129. NGDBUILD done.
  130.  
  131. Process "Translate" completed successfully
  132.  
  133. Started : "Map".
  134. Running map...
  135. Command Line: map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail -ir off -pr off -lc off -power off -o orpsoc_top_map.ncd orpsoc_top.ngd orpsoc_top.pcf
  136. Using target part "6slx45csg324-2".
  137. Mapping design into LUTs...
  138. Running directed packing...
  139. Running delay-based LUT packing...
  140. Updating timing models...
  141. WARNING:Timing:3159 - The DCM, dvi_gen0/PCLK_GEN_INST, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase
  142. relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be
  143. constrained using FROM/TO constraints.
  144. INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
  145. (.mrp).
  146. Running timing-driven placement...
  147. Total REAL time at the beginning of Placer: 43 secs
  148. Total CPU time at the beginning of Placer: 42 secs
  149.  
  150. Phase 1.1 Initial Placement Analysis
  151. Phase 1.1 Initial Placement Analysis (Checksum:6189e00b) REAL time: 46 secs
  152.  
  153. Phase 2.7 Design Feasibility Check
  154. Phase 2.7 Design Feasibility Check (Checksum:6189e00b) REAL time: 49 secs
  155.  
  156. Phase 3.31 Local Placement Optimization
  157. Phase 3.31 Local Placement Optimization (Checksum:6189e00b) REAL time: 49 secs
  158.  
  159. Phase 4.2 Initial Placement for Architecture Specific Features
  160.  
  161. Phase 4.2 Initial Placement for Architecture Specific Features
  162. (Checksum:61a790ef) REAL time: 1 mins 37 secs
  163.  
  164. Phase 5.36 Local Placement Optimization
  165. Phase 5.36 Local Placement Optimization (Checksum:61a790ef) REAL time: 1 mins 37 secs
  166.  
  167. Phase 6.30 Global Clock Region Assignment
  168. Phase 6.30 Global Clock Region Assignment (Checksum:61a790ef) REAL time: 1 mins 37 secs
  169.  
  170. Phase 7.3 Local Placement Optimization
  171. Phase 7.3 Local Placement Optimization (Checksum:61a790ef) REAL time: 1 mins 37 secs
  172.  
  173. Phase 8.5 Local Placement Optimization
  174. Phase 8.5 Local Placement Optimization (Checksum:61a790ef) REAL time: 1 mins 38 secs
  175.  
  176. Phase 9.8 Global Placement
  177. ......................
  178. ........................................................................................
  179. .............................................................................................
  180. ..............................................................................................................
  181. .............................................................................................................................................
  182. Phase 9.8 Global Placement (Checksum:1161b42c) REAL time: 5 mins 46 secs
  183.  
  184. Phase 10.5 Local Placement Optimization
  185. Phase 10.5 Local Placement Optimization (Checksum:1161b42c) REAL time: 5 mins 47 secs
  186.  
  187. Phase 11.18 Placement Optimization
  188. Phase 11.18 Placement Optimization (Checksum:e4626110) REAL time: 6 mins 15 secs
  189.  
  190. Phase 12.5 Local Placement Optimization
  191. Phase 12.5 Local Placement Optimization (Checksum:e4626110) REAL time: 6 mins 16 secs
  192.  
  193. Phase 13.34 Placement Validation
  194. Phase 13.34 Placement Validation (Checksum:f39d5de5) REAL time: 6 mins 17 secs
  195.  
  196. Total REAL time to Placer completion: 6 mins 18 secs
  197. Total CPU time to Placer completion: 6 mins 15 secs
  198. Running post-placement packing...
  199. Writing output files...
  200.  
  201. Design Summary:
  202. Number of errors: 0
  203. Number of warnings: 31
  204. Slice Logic Utilization:
  205. Number of Slice Registers: 7,289 out of 54,576 13%
  206. Number used as Flip Flops: 7,281
  207. Number used as Latches: 0
  208. Number used as Latch-thrus: 0
  209. Number used as AND/OR logics: 8
  210. Number of Slice LUTs: 13,341 out of 27,288 48%
  211. Number used as logic: 13,069 out of 27,288 47%
  212. Number using O6 output only: 10,926
  213. Number using O5 output only: 348
  214. Number using O5 and O6: 1,795
  215. Number used as ROM: 0
  216. Number used as Memory: 204 out of 6,408 3%
  217. Number used as Dual Port RAM: 176
  218. Number using O6 output only: 32
  219. Number using O5 output only: 2
  220. Number using O5 and O6: 142
  221. Number used as Single Port RAM: 0
  222. Number used as Shift Register: 28
  223. Number using O6 output only: 20
  224. Number using O5 output only: 0
  225. Number using O5 and O6: 8
  226. Number used exclusively as route-thrus: 68
  227. Number with same-slice register load: 49
  228. Number with same-slice carry load: 19
  229. Number with other load: 0
  230.  
  231. Slice Logic Distribution:
  232. Number of occupied Slices: 4,322 out of 6,822 63%
  233. Number of MUXCYs used: 1,588 out of 13,644 11%
  234. Number of LUT Flip Flop pairs used: 13,996
  235. Number with an unused Flip Flop: 7,052 out of 13,996 50%
  236. Number with an unused LUT: 655 out of 13,996 4%
  237. Number of fully used LUT-FF pairs: 6,289 out of 13,996 44%
  238. Number of unique control sets: 310
  239. Number of slice register sites lost
  240. to control set restrictions: 909 out of 54,576 1%
  241.  
  242. A LUT Flip Flop pair for this architecture represents one LUT paired with
  243. one Flip Flop within a slice. A control set is a unique combination of
  244. clock, reset, set, and enable signals for a registered element.
  245. The Slice Logic Distribution report is not meaningful if the design is
  246. over-mapped for a non-slice resource or if Placement fails.
  247.  
  248. IO Utilization:
  249. Number of bonded IOBs: 105 out of 218 48%
  250. Number of LOCed IOBs: 105 out of 105 100%
  251. IOB Master Pads: 4
  252. IOB Slave Pads: 4
  253.  
  254. Specific Feature Utilization:
  255. Number of RAMB16BWERs: 51 out of 116 43%
  256. Number of RAMB8BWERs: 18 out of 232 7%
  257. Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
  258. Number used as BUFIO2s: 1
  259. Number used as BUFIO2_2CLKs: 0
  260. Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
  261. Number used as BUFIO2FBs: 1
  262. Number used as BUFIO2FB_2CLKs: 0
  263. Number of BUFG/BUFGMUXs: 9 out of 16 56%
  264. Number used as BUFGs: 9
  265. Number used as BUFGMUX: 0
  266. Number of DCM/DCM_CLKGENs: 2 out of 8 25%
  267. Number used as DCMs: 1
  268. Number used as DCM_CLKGENs: 1
  269. Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
  270. Number of IODELAY2/IODRP2/IODRP2_MCBs: 24 out of 376 6%
  271. Number used as IODELAY2s: 0
  272. Number used as IODRP2s: 2
  273. Number used as IODRP2_MCBs: 22
  274. Number of OLOGIC2/OSERDES2s: 53 out of 376 14%
  275. Number used as OLOGIC2s: 0
  276. Number used as OSERDES2s: 53
  277. Number of BSCANs: 0 out of 4 0%
  278. Number of BUFHs: 0 out of 256 0%
  279. Number of BUFPLLs: 1 out of 8 12%
  280. Number of BUFPLL_MCBs: 1 out of 4 25%
  281. Number of DSP48A1s: 3 out of 58 5%
  282. Number of ICAPs: 0 out of 1 0%
  283. Number of MCBs: 1 out of 2 50%
  284. Number of PCILOGICSEs: 0 out of 2 0%
  285. Number of PLL_ADVs: 3 out of 4 75%
  286. Number of PMVs: 0 out of 1 0%
  287. Number of STARTUPs: 0 out of 1 0%
  288. Number of SUSPEND_SYNCs: 0 out of 1 0%
  289.  
  290. Average Fanout of Non-Clock Nets: 4.54
  291.  
  292. Peak Memory Usage: 1222 MB
  293. Total REAL time to MAP completion: 6 mins 32 secs
  294. Total CPU time to MAP completion: 6 mins 28 secs
  295.  
  296. Mapping completed.
  297. See MAP report file "orpsoc_top_map.mrp" for details.
  298.  
  299. Process "Map" completed successfully
  300.  
  301. Started : "Place & Route".
  302. Running par...
  303. Command Line: par -w -intstyle ise -ol high -mt off orpsoc_top_map.ncd orpsoc_top.ncd orpsoc_top.pcf
  304.  
  305.  
  306.  
  307. Constraints file: orpsoc_top.pcf.
  308. Loading device for application Rf_Device from file '6slx45.nph' in environment /opt/Xilinx/14.6/ISE_DS/ISE/.
  309. "orpsoc_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
  310.  
  311. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
  312. Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
  313.  
  314.  
  315. Device speed data version: "PRODUCTION 1.23 2013-06-08".
  316.  
  317.  
  318.  
  319. Device Utilization Summary:
  320.  
  321. Slice Logic Utilization:
  322. Number of Slice Registers: 7,289 out of 54,576 13%
  323. Number used as Flip Flops: 7,281
  324. Number used as Latches: 0
  325. Number used as Latch-thrus: 0
  326. Number used as AND/OR logics: 8
  327. Number of Slice LUTs: 13,341 out of 27,288 48%
  328. Number used as logic: 13,069 out of 27,288 47%
  329. Number using O6 output only: 10,926
  330. Number using O5 output only: 348
  331. Number using O5 and O6: 1,795
  332. Number used as ROM: 0
  333. Number used as Memory: 204 out of 6,408 3%
  334. Number used as Dual Port RAM: 176
  335. Number using O6 output only: 32
  336. Number using O5 output only: 2
  337. Number using O5 and O6: 142
  338. Number used as Single Port RAM: 0
  339. Number used as Shift Register: 28
  340. Number using O6 output only: 20
  341. Number using O5 output only: 0
  342. Number using O5 and O6: 8
  343. Number used exclusively as route-thrus: 68
  344. Number with same-slice register load: 49
  345. Number with same-slice carry load: 19
  346. Number with other load: 0
  347.  
  348. Slice Logic Distribution:
  349. Number of occupied Slices: 4,322 out of 6,822 63%
  350. Number of MUXCYs used: 1,588 out of 13,644 11%
  351. Number of LUT Flip Flop pairs used: 13,996
  352. Number with an unused Flip Flop: 7,052 out of 13,996 50%
  353. Number with an unused LUT: 655 out of 13,996 4%
  354. Number of fully used LUT-FF pairs: 6,289 out of 13,996 44%
  355. Number of slice register sites lost
  356. to control set restrictions: 0 out of 54,576 0%
  357.  
  358. A LUT Flip Flop pair for this architecture represents one LUT paired with
  359. one Flip Flop within a slice. A control set is a unique combination of
  360. clock, reset, set, and enable signals for a registered element.
  361. The Slice Logic Distribution report is not meaningful if the design is
  362. over-mapped for a non-slice resource or if Placement fails.
  363.  
  364. IO Utilization:
  365. Number of bonded IOBs: 105 out of 218 48%
  366. Number of LOCed IOBs: 105 out of 105 100%
  367. IOB Master Pads: 4
  368. IOB Slave Pads: 4
  369.  
  370. Specific Feature Utilization:
  371. Number of RAMB16BWERs: 51 out of 116 43%
  372. Number of RAMB8BWERs: 18 out of 232 7%
  373. Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
  374. Number used as BUFIO2s: 1
  375. Number used as BUFIO2_2CLKs: 0
  376. Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
  377. Number used as BUFIO2FBs: 1
  378. Number used as BUFIO2FB_2CLKs: 0
  379. Number of BUFG/BUFGMUXs: 9 out of 16 56%
  380. Number used as BUFGs: 9
  381. Number used as BUFGMUX: 0
  382. Number of DCM/DCM_CLKGENs: 2 out of 8 25%
  383. Number used as DCMs: 1
  384. Number used as DCM_CLKGENs: 1
  385. Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
  386. Number of IODELAY2/IODRP2/IODRP2_MCBs: 24 out of 376 6%
  387. Number used as IODELAY2s: 0
  388. Number used as IODRP2s: 2
  389. Number used as IODRP2_MCBs: 22
  390. Number of OLOGIC2/OSERDES2s: 53 out of 376 14%
  391. Number used as OLOGIC2s: 0
  392. Number used as OSERDES2s: 53
  393. Number of BSCANs: 0 out of 4 0%
  394. Number of BUFHs: 0 out of 256 0%
  395. Number of BUFPLLs: 1 out of 8 12%
  396. Number of BUFPLL_MCBs: 1 out of 4 25%
  397. Number of DSP48A1s: 3 out of 58 5%
  398. Number of ICAPs: 0 out of 1 0%
  399. Number of MCBs: 1 out of 2 50%
  400. Number of PCILOGICSEs: 0 out of 2 0%
  401. Number of PLL_ADVs: 3 out of 4 75%
  402. Number of PMVs: 0 out of 1 0%
  403. Number of STARTUPs: 0 out of 1 0%
  404. Number of SUSPEND_SYNCs: 0 out of 1 0%
  405.  
  406.  
  407. Overall effort level (-ol): High
  408. Router effort level (-rl): High
  409.  
  410. WARNING:Timing:3159 - The DCM, dvi_gen0/PCLK_GEN_INST, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase
  411. relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be
  412. constrained using FROM/TO constraints.
  413. INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
  414. Command Line Tools User Guide for information on generating a TSI report.
  415. Starting initial Timing Analysis. REAL time: 24 secs
  416. Finished initial Timing Analysis. REAL time: 24 secs
  417.  
  418. WARNING:Par:288 - The signal ac97_sdata_pad_i_IBUF has no load. PAR will not attempt to route this signal.
  419. WARNING:Par:288 - The signal vga0/wbm/data_fifo/Mram_mem1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  420. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up3/Mram_burst_data_buf1_RAMD_D1_O has no load. PAR will not attempt to route
  421. this signal.
  422. WARNING:Par:288 - The signal vga0/wbm/data_fifo/Mram_mem4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  423. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up3/Mram_burst_data_buf4_RAMD_D1_O has no load. PAR will not attempt to route
  424. this signal.
  425. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up3/Mram_burst_data_buf3_RAMD_D1_O has no load. PAR will not attempt to route
  426. this signal.
  427. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up3/Mram_burst_data_buf5_RAMD_D1_O has no load. PAR will not attempt to route
  428. this signal.
  429. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up0/Mram_burst_data_buf4_RAMD_D1_O has no load. PAR will not attempt to route
  430. this signal.
  431. WARNING:Par:288 - The signal vga0/wbm/data_fifo/Mram_mem3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  432. WARNING:Par:288 - The signal vga0/wbm/data_fifo/Mram_mem5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  433. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up1/Mram_burst_data_buf2_RAMD_D1_O has no load. PAR will not attempt to route
  434. this signal.
  435. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up1/Mram_burst_data_buf1_RAMD_D1_O has no load. PAR will not attempt to route
  436. this signal.
  437. WARNING:Par:288 - The signal vga0/pixel_generator/rgb_fifo/Mram_mem2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  438. WARNING:Par:288 - The signal vga0/pixel_generator/rgb_fifo/Mram_mem4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  439. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up0/Mram_burst_data_buf1_RAMD_D1_O has no load. PAR will not attempt to route
  440. this signal.
  441. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up0/Mram_burst_data_buf2_RAMD_D1_O has no load. PAR will not attempt to route
  442. this signal.
  443. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up0/Mram_burst_data_buf5_RAMD_D1_O has no load. PAR will not attempt to route
  444. this signal.
  445. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up0/Mram_burst_data_buf3_RAMD_D1_O has no load. PAR will not attempt to route
  446. this signal.
  447. WARNING:Par:288 - The signal vga0/wbm/data_fifo/Mram_mem2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  448. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up3/Mram_burst_data_buf2_RAMD_D1_O has no load. PAR will not attempt to route
  449. this signal.
  450. WARNING:Par:288 - The signal vga0/pixel_generator/rgb_fifo/Mram_mem1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  451. WARNING:Par:288 - The signal vga0/pixel_generator/rgb_fifo/Mram_mem3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  452. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up1/Mram_burst_data_buf4_RAMD_D1_O has no load. PAR will not attempt to route
  453. this signal.
  454. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up1/Mram_burst_data_buf3_RAMD_D1_O has no load. PAR will not attempt to route
  455. this signal.
  456. WARNING:Par:288 - The signal xilinx_ddr2_0/xilinx_ddr2_if0/wb2up1/Mram_burst_data_buf5_RAMD_D1_O has no load. PAR will not attempt to route
  457. this signal.
  458. WARNING:Par:288 - The signal spi0/rfifo/Mram_mem1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  459. WARNING:Par:288 - The signal spi0/wfifo/Mram_mem1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  460. WARNING:Par:288 - The signal uart16550_0/regs/transmitter/fifo_tx/tfifo/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this
  461. signal.
  462. WARNING:Par:288 - The signal uart16550_0/regs/receiver/fifo_rx/rfifo/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this
  463. signal.
  464. Starting Router
  465.  
  466.  
  467. Phase 1 : 83469 unrouted; REAL time: 27 secs
  468.  
  469. Phase 2 : 76310 unrouted; REAL time: 31 secs
  470. WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
  471. design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
  472. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
  473. Unroutable signal: dvi_clk pin: dvi_gen0/PCLK_GEN_INST/CLKIN
  474.  
  475.  
  476. Phase 3 : 41920 unrouted; REAL time: 58 secs
  477.  
  478. Phase 4 : 41926 unrouted; (Setup:0, Hold:74302, Component Switching Limit:0) REAL time: 1 mins 3 secs
  479.  
  480. Updating file: orpsoc_top.ncd with current fully routed design.
  481.  
  482. Phase 5 : 1 unrouted; (Setup:0, Hold:66582, Component Switching Limit:0) REAL time: 2 mins 6 secs
  483.  
  484. Phase 6 : 1 unrouted; (Setup:0, Hold:66582, Component Switching Limit:0) REAL time: 2 mins 6 secs
  485.  
  486. Phase 7 : 1 unrouted; (Setup:0, Hold:66582, Component Switching Limit:0) REAL time: 2 mins 6 secs
  487.  
  488. Phase 8 : 1 unrouted; (Setup:0, Hold:66582, Component Switching Limit:0) REAL time: 2 mins 6 secs
  489.  
  490. Phase 9 : 1 unrouted; (Setup:0, Hold:66582, Component Switching Limit:0) REAL time: 2 mins 6 secs
  491.  
  492. Phase 10 : 1 unrouted; (Setup:0, Hold:31753, Component Switching Limit:0) REAL time: 2 mins 13 secs
  493. WARNING:Route:452 -
  494. Not all timing constraints have been achieved. Please consult the `Post-Place & Route Static Timing Report' to determine the actual
  495. timing results. For suggestions on how to work around this problem go to http://support.xilinx.com and `Search Answers Database' using
  496. the text of this message.
  497.  
  498. Total REAL time to Router completion: 2 mins 13 secs
  499. Total CPU time to Router completion: 2 mins 19 secs
  500.  
  501. Partition Implementation Status
  502. -------------------------------
  503.  
  504. No Partitions were found in this design.
  505.  
  506. -------------------------------
  507.  
  508. Generating "PAR" statistics.
  509.  
  510. **************************
  511. Generating Clock Report
  512. **************************
  513.  
  514. +---------------------+--------------+------+------+------------+-------------+
  515. | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
  516. +---------------------+--------------+------+------+------------+-------------+
  517. | wb_clk | BUFGMUX_X3Y14| No | 2078 | 0.069 | 1.777 |
  518. +---------------------+--------------+------+------+------------+-------------+
  519. |xilinx_ddr2_0/xilinx | | | | | |
  520. |_ddr2_if0/ddr2_mig/c | | | | | |
  521. | 3_mcb_drp_clk | BUFGMUX_X3Y13| No | 104 | 0.085 | 1.796 |
  522. +---------------------+--------------+------+------+------------+-------------+
  523. | tck_pad_i_BUFGP | BUFGMUX_X3Y15| No | 165 | 0.067 | 1.777 |
  524. +---------------------+--------------+------+------+------------+-------------+
  525. |dvi_gen0/clk50m_bufg | | | | | |
  526. | | BUFGMUX_X2Y2| No | 29 | 0.054 | 1.769 |
  527. +---------------------+--------------+------+------+------------+-------------+
  528. | dvi_gen0/pclkx2 | BUFGMUX_X2Y1| No | 29 | 0.354 | 2.081 |
  529. +---------------------+--------------+------+------+------------+-------------+
  530. | pclk | BUFGMUX_X2Y10| No | 104 | 0.053 | 1.770 |
  531. +---------------------+--------------+------+------+------------+-------------+
  532. |xilinx_ddr2_0/xilinx | | | | | |
  533. |_ddr2_if0/ddr2_mig/m | | | | | |
  534. |emc3_infrastructure_ | | | | | |
  535. | inst/clk0_bufg | BUFGMUX_X2Y4| No | 1 | 0.000 | 1.765 |
  536. +---------------------+--------------+------+------+------------+-------------+
  537. | eth0_tx_clk_IBUF | Local| | 94 | 5.017 | 9.375 |
  538. +---------------------+--------------+------+------+------------+-------------+
  539. | eth0_rx_clk_IBUF | Local| | 107 | 8.848 | 13.898 |
  540. +---------------------+--------------+------+------+------------+-------------+
  541. |ac97_bit_clk_pad_i_I | | | | | |
  542. | BUF | Local| | 4 | 0.414 | 5.533 |
  543. +---------------------+--------------+------+------+------------+-------------+
  544. |xilinx_ddr2_0/xilinx | | | | | |
  545. |_ddr2_if0/ddr2_mig/c | | | | | |
  546. | 3_sysclk_2x | Local| | 34 | 0.704 | 1.551 |
  547. +---------------------+--------------+------+------+------------+-------------+
  548. |xilinx_ddr2_0/xilinx | | | | | |
  549. |_ddr2_if0/ddr2_mig/c | | | | | |
  550. | 3_sysclk_2x_180 | Local| | 37 | 0.723 | 1.570 |
  551. +---------------------+--------------+------+------+------------+-------------+
  552. |xilinx_ddr2_0/xilinx | | | | | |
  553. |_ddr2_if0/ddr2_mig/m | | | | | |
  554. |emc3_wrapper_inst/mc | | | | | |
  555. |b_ui_top_inst/mcb_ra | | | | | |
  556. |w_wrapper_inst/ioi_d | | | | | |
  557. | rp_clk | Local| | 22 | 0.000 | 0.002 |
  558. +---------------------+--------------+------+------+------------+-------------+
  559. | dvi_gen0/pclkx10 | Local| | 8 | 0.000 | 1.740 |
  560. +---------------------+--------------+------+------+------------+-------------+
  561. |xilinx_ddr2_0/xilinx | | | | | |
  562. |_ddr2_if0/ddr2_mig/m | | | | | |
  563. |emc3_wrapper_inst/mc | | | | | |
  564. |b_ui_top_inst/mcb_ra | | | | | |
  565. |w_wrapper_inst/idela | | | | | |
  566. | y_dqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
  567. +---------------------+--------------+------+------+------------+-------------+
  568. |xilinx_ddr2_0/xilinx | | | | | |
  569. |_ddr2_if0/ddr2_mig/m | | | | | |
  570. |emc3_wrapper_inst/mc | | | | | |
  571. |b_ui_top_inst/mcb_ra | | | | | |
  572. |w_wrapper_inst/idela | | | | | |
  573. | y_dqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
  574. +---------------------+--------------+------+------+------------+-------------+
  575. |xilinx_ddr2_0/xilinx | | | | | |
  576. |_ddr2_if0/ddr2_mig/m | | | | | |
  577. |emc3_wrapper_inst/mc | | | | | |
  578. |b_ui_top_inst/mcb_ra | | | | | |
  579. |w_wrapper_inst/idela | | | | | |
  580. | y_udqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
  581. +---------------------+--------------+------+------+------------+-------------+
  582. |xilinx_ddr2_0/xilinx | | | | | |
  583. |_ddr2_if0/ddr2_mig/m | | | | | |
  584. |emc3_wrapper_inst/mc | | | | | |
  585. |b_ui_top_inst/mcb_ra | | | | | |
  586. |w_wrapper_inst/idela | | | | | |
  587. | y_udqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
  588. +---------------------+--------------+------+------+------------+-------------+
  589.  
  590. * Net Skew is the difference between the minimum and maximum routing
  591. only delays for the net. Note this is different from Clock Skew which
  592. is reported in TRCE timing report. Clock Skew is the difference between
  593. the minimum and maximum path delays which includes logic delays.
  594.  
  595. * The fanout is the number of component pins not the individual BEL loads,
  596. for example SLICE loads not FF loads.
  597.  
  598. Timing Score: 31753 (Setup: 0, Hold: 31753, Component Switching Limit: 0)
  599.  
  600. WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
  601.  
  602. Review the timing report using Timing Analyzer (In ISE select "Post-Place &
  603. Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
  604.  
  605. Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
  606. are set in the tools for timing closure.
  607.  
  608. Use the Xilinx "SmartXplorer" script to try special combinations of
  609. options known to produce very good results.
  610.  
  611. Visit the Xilinx technical support web at http://support.xilinx.com and go to
  612. either "Troubleshoot->Tech Tips->Timing & Constraints" or "
  613. TechXclusives->Timing Closure" for tips and suggestions for meeting timing
  614. in your design.
  615.  
  616. Number of Timing Constraints that were not applied: 16
  617.  
  618. Asterisk (*) preceding a constraint indicates it was not met.
  619. This may be due to a setup or hold violation.
  620.  
  621. ----------------------------------------------------------------------------------------------------------
  622. Constraint | Check | Worst Case | Best Case | Timing | Timing
  623. | | Slack | Achievable | Errors | Score
  624. ----------------------------------------------------------------------------------------------------------
  625. * TS_eth0_tx_clk = PERIOD TIMEGRP "eth0_tx_ | SETUP | 26.846ns| 13.154ns| 0| 0
  626. clk" 25 MHz HIGH 50% PRIORITY 0 | HOLD | -1.451ns| | 38| 17578
  627. ----------------------------------------------------------------------------------------------------------
  628. * TS_eth0_rx_clk = PERIOD TIMEGRP "eth0_rx_ | SETUP | 27.334ns| 12.666ns| 0| 0
  629. clk" 25 MHz HIGH 50% PRIORITY 0 | HOLD | -1.188ns| | 34| 7714
  630. ----------------------------------------------------------------------------------------------------------
  631. * TS_dvi_gen0_pllclk2 = PERIOD TIMEGRP "dvi | SETUP | 1.293ns| 5.481ns| 0| 0
  632. _gen0_pllclk2" TS_dvi_gen0_clkfx * 2 | HOLD | -0.713ns| | 19| 6461
  633. HIGH 50% | | | | |
  634. ----------------------------------------------------------------------------------------------------------
  635. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 0.276ns| 1.599ns| 0| 0
  636. _memc3_infrastructure_inst_clk_2x_0_0 | | | | |
  637. = PERIOD TIMEGRP "xilinx_ddr | | | | |
  638. 2_0_xilinx_ddr2_if0_ddr2_mig_memc3_infras | | | | |
  639. tructure_inst_clk_2x_0_0" TS_clkg | | | | |
  640. en0_dcm0_clkfx_prebufg * 2 HIGH 50% | | | | |
  641. ----------------------------------------------------------------------------------------------------------
  642. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 0.276ns| 1.599ns| 0| 0
  643. _memc3_infrastructure_inst_clk_2x_180_0 | | | | |
  644. = PERIOD TIMEGRP "xilinx_d | | | | |
  645. dr2_0_xilinx_ddr2_if0_ddr2_mig_memc3_infr | | | | |
  646. astructure_inst_clk_2x_180_0" TS_ | | | | |
  647. clkgen0_dcm0_clkfx_prebufg * 2 PHASE 0.93 | | | | |
  648. 75 ns HIGH 50% | | | | |
  649. ----------------------------------------------------------------------------------------------------------
  650. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 0.276ns| 1.599ns| 0| 0
  651. _memc3_infrastructure_inst_clk_2x_0 = | | | | |
  652. PERIOD TIMEGRP "xilinx_ddr2_ | | | | |
  653. 0_xilinx_ddr2_if0_ddr2_mig_memc3_infrastr | | | | |
  654. ucture_inst_clk_2x_0" TS_SYS_CLK3 | | | | |
  655. / 2 HIGH 50% | | | | |
  656. ----------------------------------------------------------------------------------------------------------
  657. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 0.276ns| 1.599ns| 0| 0
  658. _memc3_infrastructure_inst_clk_2x_180 | | | | |
  659. = PERIOD TIMEGRP "xilinx_ddr | | | | |
  660. 2_0_xilinx_ddr2_if0_ddr2_mig_memc3_infras | | | | |
  661. tructure_inst_clk_2x_180" TS_SYS_ | | | | |
  662. CLK3 / 2 PHASE 0.9375 ns HIGH 50% | | | | |
  663. ----------------------------------------------------------------------------------------------------------
  664. TS_dvi_gen0_clkfx = PERIOD TIMEGRP "dvi_g | MINLOWPULSE | 8.548ns| 5.000ns| 0| 0
  665. en0_clkfx" TS_dvi_clk * 1.47619048 | | | | |
  666. HIGH 50% | | | | |
  667. ----------------------------------------------------------------------------------------------------------
  668. TS_clkgen0_pll0_clk1_prebufg = PERIOD TIM | SETUP | 0.402ns| 19.598ns| 0| 0
  669. EGRP "clkgen0_pll0_clk1_prebufg" | HOLD | 0.275ns| | 0| 0
  670. TS_clkgen0_dcm0_clk90_prebufg * 0.5 HIGH | | | | |
  671. 50% | | | | |
  672. ----------------------------------------------------------------------------------------------------------
  673. TS_sys_clk_pad_i = PERIOD TIMEGRP "sys_cl | MINLOWPULSE | 4.660ns| 5.340ns| 0| 0
  674. k_pad_i" 100 MHz HIGH 50% | | | | |
  675. ----------------------------------------------------------------------------------------------------------
  676. TS_clkgen0_dcm0_clkfx_prebufg = PERIOD TI | MINLOWPULSE | 1.416ns| 2.334ns| 0| 0
  677. MEGRP "clkgen0_dcm0_clkfx_prebufg" | | | | |
  678. TS_sys_clk_pad_i * 2.66666667 PHASE 1.8 | | | | |
  679. 75 ns HIGH 50% | | | | |
  680. ----------------------------------------------------------------------------------------------------------
  681. TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 3 | MINLOWPULSE | 1.416ns| 2.334ns| 0| 0
  682. .75 ns HIGH 50% | | | | |
  683. ----------------------------------------------------------------------------------------------------------
  684. TS_dvi_clk = PERIOD TIMEGRP "dvi_clk" TS_ | SETUP | 3.415ns| 16.097ns| 0| 0
  685. sys_clk_pad_i / 2 HIGH 50% | HOLD | 2.739ns| | 0| 0
  686. ----------------------------------------------------------------------------------------------------------
  687. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | SETUP | 4.286ns| 10.713ns| 0| 0
  688. _memc3_infrastructure_inst_mcb_drp_clk_bu | HOLD | 0.412ns| | 0| 0
  689. fg_in_0 = PERIOD TIMEGRP | | | | |
  690. "xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig_m | | | | |
  691. emc3_infrastructure_inst_mcb_drp_clk_bufg | | | | |
  692. _in_0" TS_clkgen0_dcm0_clkfx_preb | | | | |
  693. ufg * 0.25 HIGH 50% | | | | |
  694. ----------------------------------------------------------------------------------------------------------
  695. TS_clkgen0_dcm0_clk90_prebufg = PERIOD TI | MINLOWPULSE | 6.666ns| 3.334ns| 0| 0
  696. MEGRP "clkgen0_dcm0_clk90_prebufg" | | | | |
  697. TS_sys_clk_pad_i PHASE 2.5 ns HIGH 50% | | | | |
  698. ----------------------------------------------------------------------------------------------------------
  699. TS_dvi_gen0_pllclk1 = PERIOD TIMEGRP "dvi | MINPERIOD | 9.978ns| 3.570ns| 0| 0
  700. _gen0_pllclk1" TS_dvi_gen0_clkfx HIGH | | | | |
  701. 50% | | | | |
  702. ----------------------------------------------------------------------------------------------------------
  703. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 12.334ns| 2.666ns| 0| 0
  704. _memc3_infrastructure_inst_mcb_drp_clk_bu | | | | |
  705. fg_in = PERIOD TIMEGRP "x | | | | |
  706. ilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig_mem | | | | |
  707. c3_infrastructure_inst_mcb_drp_clk_bufg_i | | | | |
  708. n" TS_SYS_CLK3 / 0.25 HIGH 50% | | | | |
  709. ----------------------------------------------------------------------------------------------------------
  710. TS_CLK50M = PERIOD TIMEGRP "TNM_CLK50M" 5 | SETUP | 12.762ns| 7.238ns| 0| 0
  711. 0 MHz HIGH 50% PRIORITY 0 | HOLD | 0.396ns| | 0| 0
  712. ----------------------------------------------------------------------------------------------------------
  713. TS_wb_clk = PERIOD TIMEGRP "wb_clk" 50 MH | MINPERIOD | 16.430ns| 3.570ns| 0| 0
  714. z HIGH 50% | | | | |
  715. ----------------------------------------------------------------------------------------------------------
  716. TS_PCLKX2 = PERIOD TIMEGRP "TNM_PCLKX2" T | SETUP | 17.280ns| 2.561ns| 0| 0
  717. S_PCLK * 2 HIGH 50% | HOLD | 0.387ns| | 0| 0
  718. ----------------------------------------------------------------------------------------------------------
  719. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 27.334ns| 2.666ns| 0| 0
  720. _memc3_infrastructure_inst_clk0_bufg_in | | | | |
  721. = PERIOD TIMEGRP "xilinx_d | | | | |
  722. dr2_0_xilinx_ddr2_if0_ddr2_mig_memc3_infr | | | | |
  723. astructure_inst_clk0_bufg_in" TS_ | | | | |
  724. SYS_CLK3 / 0.125 HIGH 50% | | | | |
  725. ----------------------------------------------------------------------------------------------------------
  726. TS_xilinx_ddr2_0_xilinx_ddr2_if0_ddr2_mig | MINPERIOD | 27.334ns| 2.666ns| 0| 0
  727. _memc3_infrastructure_inst_clk0_bufg_in_0 | | | | |
  728. = PERIOD TIMEGRP "xilinx | | | | |
  729. _ddr2_0_xilinx_ddr2_if0_ddr2_mig_memc3_in | | | | |
  730. frastructure_inst_clk0_bufg_in_0" | | | | |
  731. TS_clkgen0_dcm0_clkfx_prebufg * 0.125 HI | | | | |
  732. GH 50% | | | | |
  733. ----------------------------------------------------------------------------------------------------------
  734. TS_ramra = MAXDELAY FROM TIMEGRP "bramra" | SETUP | 29.226ns| 10.456ns| 0| 0
  735. TO TIMEGRP "fddbgrp" TS_PCLK | HOLD | 0.986ns| | 0| 0
  736. ----------------------------------------------------------------------------------------------------------
  737. TS_PCLK = PERIOD TIMEGRP "TNM_PCLK" 25.2 | SETUP | 29.841ns| 9.841ns| 0| 0
  738. MHz HIGH 50% PRIORITY 0 | HOLD | 0.319ns| | 0| 0
  739. ----------------------------------------------------------------------------------------------------------
  740. TS_ramdo = MAXDELAY FROM TIMEGRP "bramgrp | SETUP | 33.415ns| 6.267ns| 0| 0
  741. " TO TIMEGRP "fddbgrp" TS_PCLK | HOLD | 0.394ns| | 0| 0
  742. ----------------------------------------------------------------------------------------------------------
  743. TS_tck_pad_i = PERIOD TIMEGRP "tck_pad_i" | SETUP | 48.478ns| 17.524ns| 0| 0
  744. 10 MHz HIGH 50% PRIORITY 0 | HOLD | 0.347ns| | 0| 0
  745. ----------------------------------------------------------------------------------------------------------
  746. TS_ac97_bit_clk_pad_i = PERIOD TIMEGRP "a | SETUP | 78.499ns| 2.881ns| 0| 0
  747. c97_bit_clk_pad_i" 12.288 MHz HIGH | HOLD | 0.372ns| | 0| 0
  748. 50% PRIORITY 0 | | | | |
  749. ----------------------------------------------------------------------------------------------------------
  750. PATH "TS_wb_to_eth0_rx_clk_path" TIG | SETUP | N/A| 3.920ns| N/A| 0
  751. ----------------------------------------------------------------------------------------------------------
  752. PATH "TS_eth0_tx_to_wb_clk_path" TIG | SETUP | N/A| 13.941ns| N/A| 0
  753. ----------------------------------------------------------------------------------------------------------
  754. PATH "TS_eth0_rx_to_wb_clk_path" TIG | SETUP | N/A| 18.029ns| N/A| 0
  755. ----------------------------------------------------------------------------------------------------------
  756. TS_dvi_gen0_pllclk0 = PERIOD TIMEGRP "dvi | N/A | N/A| N/A| N/A| N/A
  757. _gen0_pllclk0" TS_dvi_gen0_clkfx * 10 | | | | |
  758. HIGH 50% | | | | |
  759. ----------------------------------------------------------------------------------------------------------
  760. PATH "TS_eth0_rx_to_eth0_tx_clk_path" TIG | SETUP | N/A| 4.915ns| N/A| 0
  761. ----------------------------------------------------------------------------------------------------------
  762. PATH "TS_wb_to_eth0_tx_clk_path" TIG | SETUP | N/A| 7.226ns| N/A| 0
  763. ----------------------------------------------------------------------------------------------------------
  764. PATH "TS_eth0_tx_to_eth0_rx_clk_path" TIG | SETUP | N/A| 9.788ns| N/A| 0
  765. ----------------------------------------------------------------------------------------------------------
  766. PATH "TS_tck_to_wb_clk_path" TIG | SETUP | N/A| 23.351ns| N/A| 0
  767. ----------------------------------------------------------------------------------------------------------
  768. PATH "TS_wb_to_ac97_clk_path" TIG | SETUP | N/A| -0.437ns| N/A| 0
  769. ----------------------------------------------------------------------------------------------------------
  770. PATH "TS_ac97_to_wb_clk_path" TIG | SETUP | N/A| 1.993ns| N/A| 0
  771. ----------------------------------------------------------------------------------------------------------
  772. PATH "TS_wb_clk_to_pclk_path" TIG | SETUP | N/A| -1.775ns| N/A| 0
  773. ----------------------------------------------------------------------------------------------------------
  774. PATH "TS_pclk_to_wb_clk_path" TIG | SETUP | N/A| 11.344ns| N/A| 0
  775. ----------------------------------------------------------------------------------------------------------
  776. TS_PCLKX10 = PERIOD TIMEGRP "TNM_PCLKX10" | N/A | N/A| N/A| N/A| N/A
  777. TS_PCLK * 10 HIGH 50% | | | | |
  778. ----------------------------------------------------------------------------------------------------------
  779. PATH "TS_wb_to_tck_clk_path" TIG | SETUP | N/A| 7.076ns| N/A| 0
  780. ----------------------------------------------------------------------------------------------------------
  781.  
  782.  
  783. Derived Constraint Report
  784. Review Timing Report for more details on the following derived constraints.
  785. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
  786. or "Run Timing Analysis" from Timing Analyzer (timingan).
  787. Derived Constraints for TS_sys_clk_pad_i
  788. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  789. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  790. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  791. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  792. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  793. |TS_sys_clk_pad_i | 10.000ns| 5.340ns| 9.799ns| 0| 19| 0| 29258358|
  794. | TS_clkgen0_dcm0_clkfx_prebufg | 3.750ns| 2.334ns| 3.198ns| 0| 0| 0| 14070|
  795. | TS_xilinx_ddr2_0_xilinx_ddr2_| 15.000ns| 10.713ns| N/A| 0| 0| 14070| 0|
  796. | if0_ddr2_mig_memc3_infrastruc| | | | | | | |
  797. | ture_inst_mcb_drp_clk_bufg_in| | | | | | | |
  798. | _0 | | | | | | | |
  799. | TS_xilinx_ddr2_0_xilinx_ddr2_| 1.875ns| 1.599ns| N/A| 0| 0| 0| 0|
  800. | if0_ddr2_mig_memc3_infrastruc| | | | | | | |
  801. | ture_inst_clk_2x_180_0 | | | | | | | |
  802. | TS_xilinx_ddr2_0_xilinx_ddr2_| 1.875ns| 1.599ns| N/A| 0| 0| 0| 0|
  803. | if0_ddr2_mig_memc3_infrastruc| | | | | | | |
  804. | ture_inst_clk_2x_0_0 | | | | | | | |
  805. | TS_xilinx_ddr2_0_xilinx_ddr2_| 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
  806. | if0_ddr2_mig_memc3_infrastruc| | | | | | | |
  807. | ture_inst_clk0_bufg_in_0 | | | | | | | |
  808. | TS_dvi_clk | 20.000ns| 16.097ns| 16.182ns| 0| 19| 17086| 119|
  809. | TS_dvi_gen0_clkfx | 13.548ns| 5.000ns| 10.962ns| 0| 19| 0| 119|
  810. | TS_dvi_gen0_pllclk1 | 13.548ns| 3.570ns| N/A| 0| 0| 0| 0|
  811. | TS_dvi_gen0_pllclk0 | 1.355ns| N/A| N/A| 0| 0| 0| 0|
  812. | TS_dvi_gen0_pllclk2 | 6.774ns| 5.481ns| N/A| 19| 0| 119| 0|
  813. | TS_clkgen0_dcm0_clk90_prebufg | 10.000ns| 3.334ns| 9.799ns| 0| 0| 0| 29227083|
  814. | TS_clkgen0_pll0_clk1_prebufg | 20.000ns| 19.598ns| N/A| 0| 0| 29227083| 0|
  815. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  816.  
  817. Derived Constraints for TS_PCLK
  818. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  819. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  820. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  821. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  822. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  823. |TS_PCLK | 39.683ns| 9.841ns| 10.456ns| 0| 0| 13471| 152|
  824. | TS_PCLKX2 | 19.841ns| 2.561ns| N/A| 0| 0| 2| 0|
  825. | TS_PCLKX10 | 3.968ns| N/A| N/A| 0| 0| 0| 0|
  826. | TS_ramdo | 39.683ns| 6.267ns| N/A| 0| 0| 30| 0|
  827. | TS_ramra | 39.683ns| 10.456ns| N/A| 0| 0| 120| 0|
  828. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  829.  
  830. Derived Constraints for TS_SYS_CLK3
  831. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  832. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  833. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  834. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  835. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  836. |TS_SYS_CLK3 | 3.750ns| 2.334ns| 3.198ns| 0| 0| 0| 0|
  837. | TS_xilinx_ddr2_0_xilinx_ddr2_i| 15.000ns| 2.666ns| N/A| 0| 0| 0| 0|
  838. | f0_ddr2_mig_memc3_infrastructu| | | | | | | |
  839. | re_inst_mcb_drp_clk_bufg_in | | | | | | | |
  840. | TS_xilinx_ddr2_0_xilinx_ddr2_i| 1.875ns| 1.599ns| N/A| 0| 0| 0| 0|
  841. | f0_ddr2_mig_memc3_infrastructu| | | | | | | |
  842. | re_inst_clk_2x_180 | | | | | | | |
  843. | TS_xilinx_ddr2_0_xilinx_ddr2_i| 1.875ns| 1.599ns| N/A| 0| 0| 0| 0|
  844. | f0_ddr2_mig_memc3_infrastructu| | | | | | | |
  845. | re_inst_clk_2x_0 | | | | | | | |
  846. | TS_xilinx_ddr2_0_xilinx_ddr2_i| 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
  847. | f0_ddr2_mig_memc3_infrastructu| | | | | | | |
  848. | re_inst_clk0_bufg_in | | | | | | | |
  849. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  850.  
  851. 3 constraints not met.
  852. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
  853. constraint is not analyzed due to the following: No paths covered by this
  854. constraint; Other constraints intersect with this constraint; or This
  855. constraint was disabled by a Path Tracing Control. Please run the Timespec
  856. Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
  857.  
  858.  
  859. Generating Pad Report.
  860.  
  861. 1 signals are not completely routed. See the orpsoc_top.unroutes file for a list of all unrouted signals.
  862.  
  863. WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
  864. completely routed in this design. See the "orpsoc_top.unroutes" file for a list of
  865. all unrouted signals. Check for other warnings in your PAR report that might
  866. indicate why these nets are unroutable. These nets can also be evaluated
  867. in FPGA Editor by selecting "Unrouted Nets" in the List Window.
  868.  
  869. WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
  870.  
  871. Total REAL time to PAR completion: 2 mins 24 secs
  872. Total CPU time to PAR completion: 2 mins 30 secs
  873.  
  874. Peak Memory Usage: 990 MB
  875.  
  876. Placer: Placement generated during map.
  877. Routing: Completed - errors found.
  878. Timing: Completed - 91 errors found.
  879.  
  880. Number of error messages: 0
  881. Number of warning messages: 37
  882. Number of info messages: 1
  883.  
  884. Writing design to file orpsoc_top.ncd
  885.  
  886.  
  887.  
  888. PAR done!
  889.  
  890. Process "Place & Route" failed
  891. INFO:TclTasksC:1850 - process run : Generate Programming File is done.
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