`timescale 1ns/1ps

module counter_test;


logic clk,rst;
logic [3:0] result;
 logic[3:0] start;
initial begin
    clk=0;
    forever #10 clk = ~clk;
end



initial
begin
    for(logic[3:0] i = 0; i < 6; i++)
      transaction(i);
    #100 $stop;
end

 task transaction;
   input [3:0] start_;
   begin
     start = start_;
    rst = 0;
    #10 rst = 1;
    #10 $strobe("START: %d", start);
    repeat(16) #20 $strobe("Counter value: %d", result);
    end

 endtask

bin_cnt test_dev(clk, rst,start,  result);
endmodule