@ Switch to FIQ mode and keep interrupts disabled (required to have access to SPSR register)
@ NOTE:  The code following this point cannot result in a change to the FIQ mode SP

MSR     CPSR_c,#(ESAL_AR_ISR_CPSR_FIQ_MODE | ESAL_AR_ISR_CPSR_IRQ_BIT | ESAL_AR_ISR_CPSR_FIQ_BIT)

@ Get return address and SPSR from stack

LDR     lr,[r0,#ESAL_AR_STK_MIN_PC_OFFSET]
LDR     r1,[r0,#ESAL_AR_STK_MIN_SPSR_OFFSET]

@ Update SPSR

MSR     SPSR_cxsf, r1

@ Restore minimal registers

LDMIA   r0,{r0-r3}

@ Return to point of interrupt

MOVS    pc,lr