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  1. From 0766f99a3964fa4de9cbef01976ad89645755f4f Mon Sep 17 00:00:00 2001
  2. From: serus <[email protected]>
  3. Date: Fri, 6 Nov 2015 15:28:33 +0100
  4. Subject: [PATCH] custom ports
  5.  
  6. ---
  7. arch/arm/mach-mx6/board-mx6_seco_UDOO.c   | 47 +++++++++++++++++++++++++++----
  8.  arch/arm/mach-mx6/board-mx6qd_seco_UDOO.h | 30 ++++++++++----------
  9.  2 files changed, 56 insertions(+), 21 deletions(-)
  10.  
  11. diff --git a/arch/arm/mach-mx6/board-mx6_seco_UDOO.c b/arch/arm/mach-mx6/board-mx6_seco_UDOO.c
  12. index 435a50d..dbb09e2 100644
  13. --- a/arch/arm/mach-mx6/board-mx6_seco_UDOO.c
  14. +++ b/arch/arm/mach-mx6/board-mx6_seco_UDOO.c
  15. @@ -114,8 +114,8 @@
  16.  #define SSI_CH_NUMBER              1
  17.  #endif
  18.  /******************* CAN *******************/
  19. -//#define MX6_SECO_UDOO_CAN1_STBY      IMX_GPIO_NR(1, 2)
  20. -//#define MX6_SECO_UDOO_CAN1_EN            IMX_GPIO_NR(1, 4)
  21. +#define MX6_SECO_UDOO_CAN1_STBY        IMX_GPIO_NR(1, 2)
  22. +#define MX6_SECO_UDOO_CAN1_EN          IMX_GPIO_NR(1, 4)
  23.  
  24.  //#define MX6_SECO_UDOO_CAP_TCH_INT1   IMX_GPIO_NR(1, 9)
  25.  
  26. @@ -131,6 +131,38 @@ extern char *pu_reg_id;
  27.  extern struct regulator *(*get_cpu_regulator)(void);
  28.  extern void (*put_cpu_regulator)(void);
  29.  
  30. +/***********************************************************************
  31. + * SPI *
  32. + ***********************************************************************/
  33. +
  34. +// chip select pin
  35. +static int mx6q_UDOO_spi_SS0[] = {
  36. +   MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0,
  37. +};
  38. +
  39. +// this struct is added in function mx6_seco_UDOO_board_init()
  40. +static const struct spi_imx_master mx6q_UDOO_spi_data2 __initconst = {
  41. +   .chipselect = mx6q_UDOO_spi_SS0,
  42. +   .num_chipselect = ARRAY_SIZE(mx6q_UDOO_spi_SS0),
  43. +};
  44. +
  45. +// all spi devices initialization data goes in this array
  46. +static struct spi_board_info imx6_UDOO_spi_any_device[] __initdata = {
  47. +   {
  48. +       .modalias = "spidev",
  49. +       .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  50. +       .bus_num = 0,
  51. +       .chip_select = 0,
  52. +       .mode = SPI_MODE_0,
  53. +   },
  54. +};
  55. +
  56. +// this is called in function mx6_seco_UDOO_board_init()
  57. +static void spi_device_init(void) {
  58. +imx6q_add_ecspi(0, &mx6q_UDOO_spi_data2);
  59. +spi_register_board_info(imx6_UDOO_spi_any_device, ARRAY_SIZE(imx6_UDOO_spi_any_device));
  60. +}
  61. +
  62.  
  63.  /***********************************************************************
  64.   *                                   SD                                *
  65. @@ -237,9 +269,11 @@ static struct ahci_platform_data mx6q_seco_UDOO_sata_data = {
  66.   ***********************************************************************/
  67.  
  68.  static inline void mx6q_seco_UDOO_init_uart(void) {
  69. -   imx6q_add_imx_uart(0, NULL);
  70. -   imx6q_add_imx_uart(1, NULL);
  71. +        imx6q_add_imx_uart(0, NULL);
  72. +        imx6q_add_imx_uart(1, NULL);
  73. +        imx6q_add_imx_uart(2, NULL);   // added UART3 aka /dev/ttymxc2
  74.      imx6q_add_imx_uart(3, NULL);
  75. +    imx6q_add_imx_uart(4, NULL);       // added UART5 aka /dev/ttymxc4
  76.  }
  77.  
  78.  /***********************************************************************
  79. @@ -948,7 +982,7 @@ static void __init mx6_seco_UDOO_board_init(void)
  80.             ARRAY_SIZE(mx6sdl_seco_UDOO_pads));
  81.             printk("\n> UDOO dual");
  82.     }
  83. -  
  84. +
  85.  
  86.  #ifdef REVB
  87.         printk("\n> rev B ");
  88. @@ -1060,7 +1094,7 @@ static void __init mx6_seco_UDOO_board_init(void)
  89.     imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
  90.     imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
  91.     imx6q_add_asrc(&imx_asrc_data);
  92. -      //  imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_pdata);
  93. +        imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_pdata);
  94.  
  95.     /* release USB Hub reset */
  96.     gpio_set_value(MX6_UDOO_USB_HUB_RESET, 1);
  97. @@ -1099,6 +1133,7 @@ static void __init mx6_seco_UDOO_board_init(void)
  98.     imx6q_add_perfmon(0);
  99.     imx6q_add_perfmon(1);
  100.     imx6q_add_perfmon(2);
  101. +   spi_device_init();
  102.  }
  103.  
  104.  extern void __iomem *twd_base;
  105. diff --git a/arch/arm/mach-mx6/board-mx6qd_seco_UDOO.h b/arch/arm/mach-mx6/board-mx6qd_seco_UDOO.h
  106. index bfd2c4b..b1d640c 100644
  107. --- a/arch/arm/mach-mx6/board-mx6qd_seco_UDOO.h
  108. +++ b/arch/arm/mach-mx6/board-mx6qd_seco_UDOO.h
  109. @@ -25,7 +25,7 @@
  110.  #define MX6Q_PAD_GPIO_16__GPIO_7_11_CORRECT \
  111.         (IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0xB0B1))
  112.  
  113. -// internal gpios definition  
  114. +// internal gpios definition
  115.  #define MX6Q_PAD_SD2_DAT0__GPIO_MODE       IMX_GPIO_NR(1, 15)
  116.  #define MX6Q_PAD_SD2_DAT2__GPIO_MODE       IMX_GPIO_NR(1, 13)
  117.  #define MX6Q_PAD_EIM_EB2__GPIO_MODE            IMX_GPIO_NR(2, 30)
  118. @@ -327,10 +327,10 @@ static iomux_v3_cfg_t mx6qd_seco_UDOO_pads[] = {
  119.         // MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS,
  120.     MX6Q_PAD_DISP0_DAT19__GPIO_5_13,                        // pin 35
  121.         // MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD,
  122. -   MX6Q_PAD_DISP0_DAT20__GPIO_5_14,                        // pin 36
  123. -       // MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK,  
  124. -   MX6Q_PAD_DISP0_DAT21__GPIO_5_15,                        // pin 37
  125. -       // MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI,
  126. +   //MX6Q_PAD_DISP0_DAT20__GPIO_5_14,                      // pin 36
  127. +       MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK, 
  128. +   //MX6Q_PAD_DISP0_DAT21__GPIO_5_15,                      // pin 37
  129. +       MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI,
  130.     MX6Q_PAD_EIM_A16__GPIO_2_22,                            // pin 38
  131.     MX6Q_PAD_GPIO_18__GPIO_7_13,                            // pin 39
  132.     MX6Q_PAD_NANDF_D0__GPIO_2_0,                            // pin 40
  133. @@ -344,10 +344,10 @@ static iomux_v3_cfg_t mx6qd_seco_UDOO_pads[] = {
  134.     MX6Q_PAD_GPIO_19__GPIO_4_5,                             // pin 44
  135.         // MX6Q_PAD_GPIO_19__SPDIF_OUT1,
  136.         // MX6Q_PAD_GPIO_19__CCM_CLKO, 
  137. -   MX6Q_PAD_DISP0_DAT22__GPIO_5_16,                        // pin 45
  138. -       // MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO,
  139. -   MX6Q_PAD_DISP0_DAT23__GPIO_5_17,                        // pin 46
  140. -       // MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0,
  141. +   //MX6Q_PAD_DISP0_DAT22__GPIO_5_16,                      // pin 45
  142. +       MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO,
  143. +   //MX6Q_PAD_DISP0_DAT23__GPIO_5_17,                      // pin 46
  144. +       MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0,
  145.     MX6Q_PAD_EIM_D25__GPIO_3_25,                            // pin 47
  146.         // MX6Q_PAD_EIM_D25__UART3_RXD,
  147.     MX6Q_PAD_KEY_ROW1__GPIO_4_9,                            // pin 48
  148. @@ -366,10 +366,10 @@ static iomux_v3_cfg_t mx6qd_seco_UDOO_pads[] = {
  149.         // MX6Q_PAD_EIM_D24__UART3_TXD,  
  150.         // MX6Q_PAD_EIM_D24__ECSPI1_SS2,
  151.  
  152. -   MX6Q_PAD_GPIO_7__GPIO_1_7,                              // can tx
  153. -       // MX6Q_PAD_GPIO_7__CAN1_TXCAN,
  154. -   MX6Q_PAD_GPIO_8__GPIO_1_8,                              // can rx
  155. -       // MX6Q_PAD_GPIO_8__CAN1_RXCAN,
  156. +   //MX6Q_PAD_GPIO_7__GPIO_1_7,                                // can tx
  157. +       MX6Q_PAD_GPIO_7__CAN1_TXCAN,
  158. +   //MX6Q_PAD_GPIO_8__GPIO_1_8,                                // can rx
  159. +       MX6Q_PAD_GPIO_8__CAN1_RXCAN,
  160.  };
  161.  
  162.  static unsigned int mx6q_set_in_outputmode_low[] = {
  163. @@ -467,8 +467,8 @@ static unsigned int mx6q_set_in_inputmode[] = {
  164.     MX6Q_PAD_EIM_CS0__GPIO_MODE,           
  165.     MX6Q_PAD_EIM_D24__GPIO_MODE,  
  166.  
  167. -   MX6Q_PAD_GPIO_8__GPIO_MODE,
  168. -   MX6Q_PAD_GPIO_7__GPIO_MODE,
  169. +   //MX6Q_PAD_GPIO_8__GPIO_MODE,
  170. +   //MX6Q_PAD_GPIO_7__GPIO_MODE,
  171.  };
  172.  
  173.  
  174. --
  175. 1.9.1
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