#!/bin/python3

from migen import *
from migen.fhdl import verilog


L = [
    ("start_bit",1, DIR_M_TO_S),
    ("transmit_bit", 1, DIR_M_TO_S),
    ("cmd_id", 6, DIR_M_TO_S),
    ("arg", 32, DIR_M_TO_S),
    ("stb", 1, DIR_M_TO_S),
    ("crc7", 7, DIR_S_TO_M),
    ("ack", 1, DIR_S_TO_M)
]

crc7_table = [
    0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
    0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
    0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
    0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
    0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
    0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
    0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
    0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
    0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
    0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
    0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
    0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
    0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
    0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
    0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
    0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
]

"""
crc_t crc_update(crc_t crc, const void *data, size_t data_len)
{
    const unsigned char *d = (const unsigned char *)data;
    unsigned int tbl_idx;

    while (data_len--) {
        tbl_idx = ((crc << 1) ^ *d);
        crc = (crc_table[tbl_idx]) & 0x7f;

        d++;
    }
    return crc & 0x7f;
}
"""

class CRC7(Module):
    def __init__(self):
        self.slave = slave = Record(L)
        self.total = total = Cat(slave.arg, slave.cmd_id, slave.transmit_bit, slave.start_bit)
        started = Signal()
        self.bt_cnt = bt_cnt = Signal(3)
        self.crc = crc = Signal(7)
        self.comb += slave.crc7.eq(crc)
        self.sync += [
            If(~started & slave.stb,
                        crc.eq(0),
                        bt_cnt.eq(0),
                        started.eq(1),
                        slave.ack.eq(0)
            ),

            If(started,
               bt_cnt.eq(bt_cnt+1)
            ),

            If(bt_cnt == 5,
               slave.ack.eq(1),
               started.eq(0)
            )
        ]

        self.data = data = Signal(8)
        cases_data = {}
        for i in range(5):
            cases_data[i + 1] = data.eq(total[(4-i)*8 : (4-i) * 8 + 8])
        self.comb += Case(bt_cnt, cases_data)

        tbl_idx = Signal(8)
        self.comb += tbl_idx.eq(Cat(0,crc) ^ data)

        crccase = {}
        for i in range (256):
            crccase[i] = If(bt_cnt < 6, crc.eq(crc7_table[i]))
        self.sync += Case(tbl_idx, crccase)



def counter_test(dut):
    #master = Record(L)
    #yield master.connect(dut.slave)

    yield dut.slave.start_bit.eq(0)
    yield dut.slave.transmit_bit.eq(0)
    yield dut.slave.cmd_id.eq(55)
    yield dut.slave.arg.eq(0x120)
    yield dut.slave.stb.eq(1)
    yield
    yield dut.slave.stb.eq(0)
    for i in range(20):
        print(format((yield dut.total), '06x'))
        print((yield dut.bt_cnt))
        print(format((yield dut.data), '02x'))
        print(format((yield dut.crc), '02x'))
        print((yield dut.slave.ack))
        print("\n")
        yield





if __name__ == "__main__":
    dut = CRC7()
    run_simulation(dut, counter_test(dut), vcd_name="basic1.vcd")




#print(verilog.convert(CRC7()))
#print(layout_len(L))
#print(layout_partial(L, "cmd_id"))