Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- //23 cntr, clk is 16 MHz
- reg [22:0] cntr;
- //*TODO*
- always@(posedge clk)
- begin
- if(rst)
- cntr<=0;
- else
- cntr<=cntr+1;
- end
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement