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  1. /*
  2. * Copyright 2013 http://www.starterkit.ru
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11.  
  12. /dts-v1/;
  13.  
  14. memgpu: /memreserve/ 0x7C000000 0x4000000;
  15.  
  16. /include/ "imx53.dtsi"
  17.  
  18. / {
  19. model = "i.mx53 starterkit";
  20. compatible = "sk,imx53-sk", "fsl,imx53";
  21.  
  22. memory {
  23. reg = <0x70000000 0x10000000>; /* Up to 256MB */
  24. };
  25.  
  26. spi_lvds0 {
  27. compatible = "spi-gpio";
  28. status = "okay";
  29. gpio-sck = <&gpio2 16 0>;
  30. gpio-miso = <&gpio2 22 0>;
  31. gpio-mosi = <&gpio2 17 0>;
  32. cs-gpios = <&gpio2 20 0>;
  33. num-chipselects = <1>;
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36.  
  37. tsc2046@0 {
  38. compatible = "ti,tsc2046";
  39. reg = <0>;
  40. spi-max-frequency = <1000000>;
  41. /* pen irq is GPIO3_22 */
  42. interrupt-parent = <&gpio3>;
  43. interrupts = <22 0x2>;
  44. pendown-gpio = <&gpio3 22 0>;
  45. vcc-supply = <&reg_3p3v>;
  46.  
  47. ti,x-min = <150>;
  48. ti,x-max = <3830>;
  49. ti,y-min = <190>;
  50. ti,y-max = <3830>;
  51.  
  52. linux,wakeup;
  53. };
  54. };
  55.  
  56. regulators {
  57. compatible = "simple-bus";
  58.  
  59. reg_3p3v: 3p3v {
  60. compatible = "regulator-fixed";
  61. regulator-name = "3P3V";
  62. regulator-min-microvolt = <3300000>;
  63. regulator-max-microvolt = <3300000>;
  64. regulator-always-on;
  65. };
  66. };
  67.  
  68. reg_otgvbus:fixed@1 {
  69. compatible = "regulator-fixed";
  70. regulator-name = "vbus-supply";
  71. regulator-min-microvolt = <5000000>;
  72. regulator-max-microvolt = <5000000>;
  73. gpio = <&gpio2 24 0>;
  74. enable-active-high;
  75. };
  76.  
  77. reg_hshvbus:fixed@2 {
  78. compatible = "regulator-fixed";
  79. regulator-name = "vbus-supply";
  80. regulator-min-microvolt = <5000000>;
  81. regulator-max-microvolt = <5000000>;
  82. gpio = <&gpio2 29 0>;
  83. enable-active-high;
  84. };
  85.  
  86.  
  87.  
  88. disp1: display@di0 {
  89. compatible = "fsl,imx-parallel-display";
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&pinctrl_disp1_1>;
  92. crtcs = <&ipu 0>;
  93. interface-pix-fmt = "rgb18";
  94. status = "okay";
  95. display-timings {
  96. MI0570KT1 {
  97. clock-frequency = <25000000>;
  98. hactive = <640>;
  99. vactive = <480>;
  100. hfront-porch = <16>;
  101. hback-porch = <114>;
  102. hsync-len = <30>;
  103. vback-porch = <32>;
  104. vfront-porch = <10>;
  105. vsync-len = <3>;
  106. pixelclk-active = <1>;
  107. hsync-active = <0>;
  108. vsync-active = <0>;
  109. de-active = <1>;
  110. };
  111. };
  112. };
  113.  
  114. sound {
  115. compatible = "sk,imx53-sk-sgtl5000",
  116. "fsl,imx-audio-sgtl5000";
  117. model = "imx53-sk-sgtl5000";
  118. ssi-controller = <&ssi2>;
  119. audio-codec = <&tlv320aic23>;
  120. audio-routing =
  121. "MICIN", "Mic Jack",
  122. "Headphone Jack", "LHPOUT",
  123. "Headphone Jack", "RHPOUT";
  124. mux-int-port = <2>;
  125. mux-ext-port = <4>;
  126. };
  127. };
  128.  
  129. &ldb {
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&pinctrl_lvds1_1>;
  132. /*status = "okay";*/
  133.  
  134. lvds-channel@0 {
  135. status = "okay";
  136. fsl,data-mapping = "spwg";
  137. fsl,data-width = <24>;
  138.  
  139. display-timings {
  140. timing0: 800x480 {
  141. /* SK-800x480-LVDS */
  142. clock-frequency = <33300000>;
  143. hactive = <800>;
  144. vactive = <480>;
  145. hfront-porch = <210>;
  146. hback-porch = <46>;
  147. hsync-len = <5>;
  148. vback-porch = <23>;
  149. vfront-porch = <22>;
  150. vsync-len = <5>;
  151. };
  152. };
  153. };
  154.  
  155. lvds-channel@1 {
  156. /*
  157. * enable this to support second LVDS display, clone of first
  158. * display
  159. */
  160. /* status = "okay"; */
  161. fsl,data-mapping = "spwg";
  162. fsl,data-width = <24>;
  163. display-timings = <&timing0>;
  164. };
  165. };
  166.  
  167. &iomuxc {
  168. pinctrl-names = "default";
  169. pinctrl-0 = <&pinctrl_hog>;
  170.  
  171. hog {
  172. pinctrl_hog: hoggrp {
  173. fsl,pins = <
  174. 604 0x80000000 /* MX53_PAD_EIM_CS0__GPIO2_23 (ADV_PD) */
  175. 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 (ADV_RST) */
  176. 608 0x80000000 /* MX53_PAD_EIM_CS1__GPIO2_24 (OTG_PWR) */
  177. 633 0x80000000 /* MX53_PAD_EIM_EB1__GPIO2_29 (USBH_PWR) */
  178. 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 (ETH_PHY_RST) */
  179. 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 (SD1_CD) */
  180. 633 0x80000000 /* MX53_PAD_EIM_EB1__GPIO2_29 (USBH_PWR) */
  181. 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (SSI_MCLK) */
  182. 574 0x80000000 /* MX53_PAD_EIM_A21__GPIO2_17 (TS0_MOSI) */
  183. 599 0x80000000 /* MX53_PAD_EIM_A16__GPIO2_22 (TS0_MISO) */
  184. 569 0x80000000 /* MX53_PAD_EIM_A22__GPIO2_16 (TS0_SCK) */
  185. 589 0x80000000 /* MX53_PAD_EIM_A18__GPIO2_20 (TS0_CS) */
  186. 472 0x80000000 /* MX53_PAD_EIM_D22__GPIO3_22 (TS0_PENIRQ) */
  187. >;
  188. };
  189. };
  190.  
  191. i2c2 {
  192. pinctrl_i2c2_1: i2c2grp-1 {
  193. fsl,pins = <
  194. 428 0xc0000000 /* MX53_PAD_EIM_EB2__I2C2_SCL */
  195. 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
  196. >;
  197. };
  198. };
  199.  
  200. audmux {
  201. pinctrl_audmux_1: audmuxgrp-1 {
  202. fsl,pins = <
  203. 1065 0x80000000 /* MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD */
  204. 1059 0x80000000 /* MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS */
  205. 1053 0x80000000 /* MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD */
  206. 1047 0x80000000 /* MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC */
  207. >;
  208. };
  209. };
  210.  
  211. lvds1 {
  212. pinctrl_lvds1_1: lvds1-grp1 {
  213. fsl,pins = <
  214. 730 0x80000000 /* MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
  215. 732 0x80000000 /* MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
  216. 734 0x80000000 /* MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
  217. 736 0x80000000 /* MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
  218. 738 0x80000000 /* MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
  219. >;
  220. };
  221. };
  222.  
  223. csi {
  224. pinctrl_csi_1: csigrp-1 {
  225. fsl,pins = <
  226. 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
  227. 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
  228. 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
  229. 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
  230. 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
  231. 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
  232. 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
  233. 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
  234. 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
  235. 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
  236. 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
  237. >;
  238. };
  239. };
  240.  
  241. disp1 {
  242. pinctrl_disp1_1: disp1-grp1 {
  243. fsl,pins = < 79 0x80000000 /* DISP0_CLK */
  244. 85 0x80000000 /* DISP0_DRDY */
  245. 91 0x80000000 /* DISP0_HSYNC */
  246. 97 0x80000000 /* DISP0_VSYNC */
  247. 269 0x80000000 /* DISP0_DAT_23 */
  248. 262 0x80000000 /* DISP0_DAT_22 */
  249. 255 0x80000000 /* DISP0_DAT_21 */
  250. 248 0x80000000 /* DISP0_DAT_20 */
  251. 240 0x80000000 /* DISP0_DAT_19 */
  252. 232 0x80000000 /* DISP0_DAT_18 */
  253. 225 0x80000000 /* DISP0_DAT_17 */
  254. 217 0x80000000 /* DISP0_DAT_16 */
  255. 210 0x80000000 /* DISP0_DAT_15 */
  256. 204 0x80000000 /* DISP0_DAT_14 */
  257. 198 0x80000000 /* DISP0_DAT_13 */
  258. 192 0x80000000 /* DISP0_DAT_12 */
  259. 186 0x80000000 /* DISP0_DAT_11 */
  260. 180 0x80000000 /* DISP0_DAT_10 */
  261. 173 0x80000000 /* DISP0_DAT_9 */
  262. 166 0x80000000 /* DISP0_DAT_8 */
  263. 159 0x80000000 /* DISP0_DAT_7 */
  264. 152 0x80000000 /* DISP0_DAT_6 */
  265. 145 0x80000000 /* DISP0_DAT_5 */
  266. 138 0x80000000 /* DISP0_DAT_4 */
  267. 131 0x80000000 /* DISP0_DAT_3 */
  268. 124 0x80000000 /* DISP0_DAT_2 */
  269. 117 0x80000000 /* DISP0_DAT_1 */
  270. 110 0x80000000>; /* DISP0_DAT_0 */
  271. };
  272. };
  273. };
  274.  
  275. &gpu {
  276. mem = <0x7C000000 0x4000000>;
  277. };
  278.  
  279. &nfc {
  280. status = "okay";
  281. nand-bus-width = <8>;
  282. nand-ecc-mode = "hw";
  283. #address-cells = <1>;
  284. #size-cells = <1>;
  285.  
  286. partition@0 {
  287. label = "bootloader";
  288. reg = <0x0000000 0x00100000>;
  289. };
  290.  
  291. partition@100000 {
  292. label = "environment";
  293. reg = <0x00100000 0x00080000>;
  294. };
  295.  
  296. partition@180000 {
  297. label = "redundant-environment";
  298. reg = <0x00180000 0x00080000>;
  299. };
  300.  
  301. partition@200000 {
  302. label = "kernel";
  303. reg = <0x00200000 0x00400000>;
  304. };
  305.  
  306. partition@600000 {
  307. label = "fdt";
  308. reg = <0x00600000 0x00020000>;
  309. };
  310.  
  311. partition@620000 {
  312. label = "ramdisk";
  313. reg = <0x00620000 0x00800000>;
  314. };
  315.  
  316. partition@e20000 {
  317. label = "filesystem";
  318. reg = <0x00e20000 0x0f1e0000>;
  319. };
  320. };
  321.  
  322. &audmux {
  323. pinctrl-names = "default";
  324. pinctrl-0 = <&pinctrl_audmux_1>;
  325. status = "okay";
  326. };
  327.  
  328. &i2c2 {
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&pinctrl_i2c2_1>;
  331. status = "okay";
  332.  
  333. tlv320aic23: codec@1a {
  334. compatible = "ti,tlv320aic23";
  335. reg = <0x1a>;
  336. clocks = <&clks 150>;
  337. };
  338.  
  339. ds1338: rtc@68 {
  340. compatible = "dallas,ds1338";
  341. reg = <0x68>;
  342. };
  343.  
  344. pcf8563: rtc@51 {
  345. compatible = "nxp,pcf8563";
  346. reg = <0x51>;
  347. };
  348. };
  349.  
  350. &fec {
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_fec_1>;
  353. phy-mode = "rmii";
  354. phy-reset-gpios = <&gpio1 1 0>;
  355. status = "okay";
  356. };
  357.  
  358. &esdhc1 {
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_esdhc1_1>;
  361. vmmc-supply = <&reg_3p3v>;
  362. cd-gpios = <&gpio3 14 0>;
  363. status = "okay";
  364. };
  365.  
  366. &usbotg {
  367. dr_mode = "host";
  368. vbus-supply = <&reg_otgvbus>;
  369. status = "okay";
  370. };
  371.  
  372. &usbh1 {
  373. vbus-supply = <&reg_hshvbus>;
  374. status = "okay";
  375. };
  376.  
  377. &uart1 {
  378. pinctrl-names = "default";
  379. pinctrl-0 = <&pinctrl_uart1_2>;
  380. status = "okay";
  381. };
  382.  
  383. /*
  384. &uart2 {
  385. status = "okay";
  386. };
  387.  
  388. &uart3 {
  389. status = "okay";
  390. };
  391.  
  392. &uart4 {
  393. status = "okay";
  394. };
  395.  
  396. &uart5 {
  397. status = "okay";
  398. };
  399. */
  400.  
  401.  
  402. &ssi2 {
  403. fsl,mode = "i2s-slave";
  404. status = "okay";
  405. };
  406.  
  407. &can1 {
  408. pinctrl-names = "default";
  409. pinctrl-0 = <&pinctrl_can1_1>;
  410. status = "okay";
  411. };
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