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  1. oprofile: available events for CPU type "AMD64 family15h"
  2.  
  3. See BIOS and Kernel Developer's Guide for AMD Family 15h Processors
  4. For architectures using unit masks, you may be able to specify
  5. unit masks by name. See 'opcontrol' man page for more details.
  6.  
  7. DISPATCHED_FPU_OPS: (counter: 3)
  8. FPU Pipe Assignment (min count: 500)
  9. Unit masks (default 0xff)
  10. ----------
  11. 0x01: Total number uops assigned to Pipe 0
  12. 0x02: Total number uops assigned to Pipe 1
  13. 0x04: Total number uops assigned to Pipe 2
  14. 0x08: Total number uops assigned to Pipe 3
  15. 0x10: Total number dual-pipe uops assigned to Pipe 0
  16. 0x20: Total number dual-pipe uops assigned to Pipe 1
  17. 0x40: Total number dual-pipe uops assigned to Pipe 2
  18. 0x80: Total number dual-pipe uops assigned to Pipe 3
  19. 0xff: All ops
  20. CYCLES_FPU_EMPTY: (counter: 3, 4, 5)
  21. FP Scheduler Empty (min count: 500)
  22. RETIRED_SSE_OPS: (counter: 3)
  23. Retired SSE/BNI Ops (min count: 500)
  24. Unit masks (default 0xff)
  25. ----------
  26. 0x01: Single Precision add/subtract FLOPS
  27. 0x02: Single precision multiply FLOPS
  28. 0x04: Single precision divide/square root FLOPS
  29. 0x08: Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS
  30. 0x10: Double precision add/subtract FLOPS
  31. 0x20: Double precision multiply FLOPS
  32. 0x40: Double precision divide/square root FLOPS
  33. 0x80: Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS
  34. MOVE_SCALAR_OPTIMIZATION: (counter: 3)
  35. Number of Move Elimination and Scalar Op Optimization (min count: 500)
  36. Unit masks (default 0xc)
  37. ----------
  38. 0x01: Number of SSE Move Ops
  39. 0x02: Number of SSE Move Ops eliminated
  40. 0x04: Number of Ops that are candidates for optimization
  41. 0x08: Number of Scalar ops optimized
  42. RETIRED_SERIALIZING_OPS: (counter: 3, 4, 5)
  43. Retired Serializing Ops (min count: 500)
  44. Unit masks (default 0xf)
  45. ----------
  46. 0x01: SSE bottom-executing uops retired
  47. 0x02: SSE control word mispredict traps due to mispredictions
  48. 0x04: x87 bottom-executing uops retired
  49. 0x08: x87 control word mispredict traps due to mispredictions
  50. BOTTOM_EXECUTE_OP: (counter: 3, 4, 5)
  51. Number of Cycles that a Bottom-Execute uop is in the FP Scheduler (min count: 500)
  52. SEGMENT_REGISTER_LOADS: (counter: all)
  53. Segment Register Loads (min count: 500)
  54. Unit masks (default 0x7f)
  55. ----------
  56. 0x01: ES register
  57. 0x02: CS register
  58. 0x04: SS register
  59. 0x08: DS register
  60. 0x10: FS register
  61. 0x20: GS register
  62. 0x40: HS register
  63. PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE: (counter: all)
  64. Pipeline Restart Due to Self-Modifying Code (min count: 500)
  65. PIPELINE_RESTART_DUE_TO_PROBE_HIT: (counter: all)
  66. Pipeline Restart Due to Probe Hit (min count: 500)
  67. LOAD_Q_STORE_Q_FULL: (counter: 0, 1, 2)
  68. Load Queue/Store Queue Full (min count: 500)
  69. Unit masks (default 0x3)
  70. ----------
  71. 0x01: Cycles that the load buffer is full
  72. 0x02: Cycles that the store buffer is full
  73. LOCKED_OPS: (counter: all)
  74. Locked Operations (min count: 500)
  75. Unit masks (default 0x1)
  76. ----------
  77. 0x01: Number of locked instructions executed
  78. 0x04: Cycles spent non-speculative phase (including cache miss penalty)
  79. 0x08: Cycles waiting for a cache hit (cache miss penalty)
  80. RETIRED_CLFLUSH_INSTRUCTIONS: (counter: all)
  81. Retired CLFLUSH Instructions (min count: 500)
  82. RETIRED_CPUID_INSTRUCTIONS: (counter: all)
  83. Retired CPUID Instructions (min count: 500)
  84. LS_DISPATCH: (counter: all)
  85. LS Dispatch (min count: 500)
  86. Unit masks (default 0x7)
  87. ----------
  88. 0x01: Loads
  89. 0x02: Stores
  90. 0x04: Load-op-Stores
  91. CANCELLED_STORE_TO_LOAD: (counter: all)
  92. Canceled Store to Load Forward Operations (min count: 500)
  93. Unit masks (default 0x1)
  94. ----------
  95. 0x01: Store is smaller than load or different starting byte but partial overlap
  96. SMIS_RECEIVED: (counter: all)
  97. SMIs Received (min count: 500)
  98. EXECUTED_CFLUSH_INST: (counter: all)
  99. Executed CLFLUSH Instructions (min count: 500)
  100. DATA_CACHE_ACCESSES: (counter: all)
  101. Data Cache Accesses (min count: 500)
  102. DATA_CACHE_MISSES: (counter: all)
  103. Data Cache Misses (min count: 500)
  104. Unit masks (default 0x1)
  105. ----------
  106. 0x01: First data cache miss or streaming store to a 64B cache line
  107. 0x02: First streaming store to a 64B cache line
  108. DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE: (counter: all)
  109. Data Cache Refills from L2 or System (min count: 500)
  110. Unit masks (default 0xb)
  111. ----------
  112. 0x01: Fill with good data. (Final valid status is valid)
  113. 0x02: Early valid status turned out to be invalid
  114. 0x08: Fill with read data error
  115. DATA_CACHE_REFILLS_FROM_NORTHBRIDGE: (counter: 0, 1, 2)
  116. Data Cache Refills from System (min count: 500)
  117. UNIFIED_TLB_HIT: (counter: 0, 1, 2)
  118. Unified TLB Hit (min count: 50000)
  119. Unit masks (default 0x77)
  120. ----------
  121. 0x01: 4 KB unified TLB hit for data
  122. 0x02: 2 MB unified TLB hit for data
  123. 0x04: 1 GB unified TLB hit for data
  124. 0x10: 4 KB unified TLB hit for instruction
  125. 0x20: 2 MB unified TLB hit for instruction
  126. 0x40: 1 GB unified TLB hit for instruction
  127. 0x07: All DTLB hits
  128. 0x70: All ITLB hits
  129. 0x77: All DTLB and ITLB hits
  130. UNIFIED_TLB_MISS: (counter: 0, 1, 2)
  131. Unified TLB Miss (min count: 500)
  132. Unit masks (default 0x77)
  133. ----------
  134. 0x01: 4 KB unified TLB miss for data
  135. 0x02: 2 MB unified TLB miss for data
  136. 0x04: 1 GB unified TLB miss for data
  137. 0x10: 4 KB unified TLB miss for instruction
  138. 0x20: 2 MB unified TLB miss for instruction
  139. 0x40: 1 GB unified TLB miss for instruction
  140. 0x07: All DTLB misses
  141. 0x70: All ITLB misses
  142. 0x77: All DTLB and ITLB misses
  143. MISALIGNED_ACCESSES: (counter: all)
  144. Misaligned Accesses (min count: 500)
  145. PREFETCH_INSTRUCTIONS_DISPATCHED: (counter: all)
  146. Prefetch Instructions Dispatched (min count: 500)
  147. Unit masks (default 0x7)
  148. ----------
  149. 0x01: Load (Prefetch, PrefetchT0/T1/T2)
  150. 0x02: Store (PrefetchW)
  151. 0x04: NTA (PrefetchNTA)
  152. INEFFECTIVE_SW_PREFETCHES: (counter: all)
  153. Ineffective Software Prefetches (min count: 500)
  154. Unit masks (default 0x9)
  155. ----------
  156. 0x01: Software prefetch hit in L1 data cache
  157. 0x08: Software prefetch hit in the L2
  158. MEMORY_REQUESTS: (counter: 0, 1, 2)
  159. Memory Requests by Type (min count: 500)
  160. Unit masks (default 0x83)
  161. ----------
  162. 0x01: Requests to non-cacheable (UC) memory
  163. 0x02: Requests to write-combining (WC) memory
  164. 0x80: Streaming store (SS) requests
  165. DATA_PREFETCHER: (counter: 0, 1, 2)
  166. Data Prefetcher (min count: 500)
  167. Unit masks (default 0x2)
  168. ----------
  169. 0x02: Prefetch attempts
  170. MAB_REQS: (counter: 0, 1, 2)
  171. MAB Requests (min count: 500)
  172. Unit masks (default 0x1)
  173. ----------
  174. 0x01: MAB ID bit 0
  175. 0x02: MAB ID bit 1
  176. 0x04: MAB ID bit 2
  177. 0x08: MAB ID bit 3
  178. 0x10: MAB ID bit 4
  179. 0x20: MAB ID bit 5
  180. 0x40: MAB ID bit 6
  181. 0x80: MAB ID bit 7
  182. MAB_WAIT: (counter: 0, 1, 2)
  183. MAB Wait Cycles (min count: 500)
  184. Unit masks (default 0x1)
  185. ----------
  186. 0x01: MAB ID bit 0
  187. 0x02: MAB ID bit 1
  188. 0x04: MAB ID bit 2
  189. 0x08: MAB ID bit 3
  190. 0x10: MAB ID bit 4
  191. 0x20: MAB ID bit 5
  192. 0x40: MAB ID bit 6
  193. 0x80: MAB ID bit 7
  194. SYSTEM_READ_RESPONSES: (counter: 0, 1, 2)
  195. Response From System on Cache Refills (min count: 500)
  196. Unit masks (default 0x3f)
  197. ----------
  198. 0x01: Exclusive
  199. 0x02: Modified
  200. 0x04: Shared
  201. 0x08: Owned
  202. 0x10: Data Error
  203. 0x20: Modified unwritten
  204. OCTWORD_WRITE_TRANSFERS: (counter: 0, 1, 2)
  205. Octwords Written to System (min count: 500)
  206. Unit masks (default 0x1)
  207. ----------
  208. 0x01: Octword write transfer
  209. CPU_CLK_UNHALTED: (counter: 0, 1, 2)
  210. CPU Clocks not Halted (min count: 50000)
  211. REQUESTS_TO_L2: (counter: 0, 1, 2)
  212. Requests to L2 Cache (min count: 500)
  213. Unit masks (default 0x47)
  214. ----------
  215. 0x01: IC fill
  216. 0x02: DC fill
  217. 0x04: TLB fill (page table walks)
  218. 0x08: NB probe request
  219. 0x10: Canceled request
  220. 0x40: L2 cache prefetcher request
  221. L2_CACHE_MISS: (counter: 0, 1, 2)
  222. L2 Cache Misses (min count: 500)
  223. Unit masks (default 0x17)
  224. ----------
  225. 0x01: IC fill
  226. 0x02: DC fill (includes possible replays, whereas PMCx041 does not)
  227. 0x04: TLB page table walks
  228. 0x10: L2 cache prefetcher request
  229. L2_CACHE_FILL_WRITEBACK: (counter: 0, 1, 2)
  230. L2 Fill/Writeback (min count: 500)
  231. Unit masks (default 0x7)
  232. ----------
  233. 0x01: L2 fills from system
  234. 0x02: L2 Writebacks to system (Clean and Dirty)
  235. 0x04: L2 Clean Writebacks to system
  236. PAGE_SPLINTERING: (counter: 0, 1, 2)
  237. Page Splintering (min count: 500)
  238. Unit masks (default 0x7)
  239. ----------
  240. 0x01: Guest page size is larger than host page size when nested paging is enabled
  241. 0x02: Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region
  242. 0x04: Host page size is larger than the guest page size
  243. L2_PREFETCHER_TRIGGER: (counter: 0, 1, 2)
  244. L2 Prefetcher Trigger Events (min count: 500)
  245. Unit masks (default 0x3)
  246. ----------
  247. 0x01: Load L1 miss seen by prefetcher
  248. 0x02: Store L1 miss seen by prefetcher
  249. INSTRUCTION_CACHE_FETCHES: (counter: 0, 1, 2)
  250. Instruction Cache Fetches (min count: 500)
  251. INSTRUCTION_CACHE_MISSES: (counter: 0, 1, 2)
  252. Instruction Cache Misses (min count: 500)
  253. INSTRUCTION_CACHE_REFILLS_FROM_L2: (counter: 0, 1, 2)
  254. Instruction Cache Refills from L2 (min count: 500)
  255. INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM: (counter: 0, 1, 2)
  256. Instruction Cache Refills from System (min count: 500)
  257. L1_ITLB_MISS_AND_L2_ITLB_HIT: (counter: 0, 1, 2)
  258. L1 ITLB Miss, L2 ITLB Hit (min count: 500)
  259. L1_ITLB_MISS_AND_L2_ITLB_MISS: (counter: 0, 1, 2)
  260. L1 ITLB Miss, L2 ITLB Miss (min count: 500)
  261. Unit masks (default 0x7)
  262. ----------
  263. 0x01: Instruction fetches to a 4K page
  264. 0x02: Instruction fetches to a 2M page
  265. 0x04: Instruction fetches to a 1G page
  266. PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE: (counter: 0, 1, 2)
  267. Pipeline Restart Due to Instruction Stream Probe (min count: 500)
  268. INSTRUCTION_FETCH_STALL: (counter: 0, 1, 2)
  269. Instruction Fetch Stall (min count: 500)
  270. RETURN_STACK_HITS: (counter: 0, 1, 2)
  271. Return Stack Hits (min count: 500)
  272. RETURN_STACK_OVERFLOWS: (counter: 0, 1, 2)
  273. Return Stack Overflows (min count: 500)
  274. INSTRUCTION_CACHE_VICTIMS: (counter: 0, 1, 2)
  275. Instruction Cache Victims (min count: 500)
  276. INSTRUCTION_CACHE_INVALIDATED: (counter: 0, 1, 2)
  277. Instruction Cache Lines Invalidated (min count: 500)
  278. Unit masks (default 0xf)
  279. ----------
  280. 0x01: Non-SMC invalidating probe that missed on in-flight instructions
  281. 0x02: Non-SMC invalidating probe that hit on in-flight instructions
  282. 0x04: SMC invalidating probe that missed on in-flight instructions
  283. 0x08: SMC invalidating probe that hit on in-flight instructions
  284. ITLB_RELOADS: (counter: 0, 1, 2)
  285. ITLB Reloads (min count: 500)
  286. ITLB_RELOADS_ABORTED: (counter: 0, 1, 2)
  287. ITLB Reloads Aborted (min count: 500)
  288. RETIRED_INSTRUCTIONS: (counter: all)
  289. Retired Instructions (min count: 50000)
  290. RETIRED_UOPS: (counter: all)
  291. Retired uops (min count: 50000)
  292. RETIRED_BRANCH_INSTRUCTIONS: (counter: all)
  293. Retired Branch Instructions (min count: 500)
  294. RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS: (counter: all)
  295. Retired Mispredicted Branch Instructions (min count: 500)
  296. RETIRED_TAKEN_BRANCH_INSTRUCTIONS: (counter: all)
  297. Retired Taken Branch Instructions (min count: 500)
  298. RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED: (counter: all)
  299. Retired Taken Branch Instructions Mispredicted (min count: 500)
  300. RETIRED_FAR_CONTROL_TRANSFERS: (counter: all)
  301. Retired Far Control Transfers (min count: 500)
  302. RETIRED_BRANCH_RESYNCS: (counter: all)
  303. Retired Branch Resyncs (min count: 500)
  304. RETIRED_NEAR_RETURNS: (counter: all)
  305. Retired Near Returns (min count: 500)
  306. RETIRED_NEAR_RETURNS_MISPREDICTED: (counter: all)
  307. Retired Near Returns Mispredicted (min count: 500)
  308. RETIRED_INDIRECT_BRANCHES_MISPREDICTED: (counter: all)
  309. Retired Indirect Branches Mispredicted (min count: 500)
  310. RETIRED_MMX_FP_INSTRUCTIONS: (counter: all)
  311. Retired MMX/FP Instructions (min count: 500)
  312. Unit masks (default 0x7)
  313. ----------
  314. 0x01: x87 instructions
  315. 0x02: MMX(tm) instructions
  316. 0x04: SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)
  317. INTERRUPTS_MASKED_CYCLES: (counter: all)
  318. Interrupts-Masked Cycles (min count: 500)
  319. INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING: (counter: all)
  320. Interrupts-Masked Cycles with Interrupt Pending (min count: 500)
  321. INTERRUPTS_TAKEN: (counter: all)
  322. Interrupts Taken (min count: 500)
  323. DECODER_EMPTY: (counter: 0, 1, 2)
  324. Decoder Empty (min count: 500)
  325. DISPATCH_STALLS: (counter: 0, 1, 2)
  326. Dispatch Stalls (min count: 500)
  327. DISPATCH_STALL_FOR_SERIALIZATION: (counter: 0, 1, 2)
  328. Microsequencer Stall due to Serialization (min count: 500)
  329. DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL: (counter: 0, 1, 2)
  330. Dispatch Stall for Instruction Retire Q Full (min count: 500)
  331. DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL: (counter: 0, 1, 2)
  332. Dispatch Stall for Integer Scheduler Queue Full (min count: 500)
  333. DISPATCH_STALL_FOR_FPU_FULL: (counter: 0, 1, 2)
  334. Dispatch Stall for FP Scheduler Queue Full (min count: 500)
  335. DISPATCH_STALL_FOR_LDQ_FULL: (counter: 0, 1, 2)
  336. Dispatch Stall for LDQ Full (min count: 500)
  337. MICROSEQ_STALL_WAITING_FOR_ALL_QUIET: (counter: 0, 1, 2)
  338. Microsequencer Stall Waiting for All Quiet (min count: 500)
  339. FPU_EXCEPTIONS: (counter: all)
  340. FPU Exceptions (min count: 500)
  341. Unit masks (default 0x1f)
  342. ----------
  343. 0x01: Total microfaults
  344. 0x02: Total microtraps
  345. 0x04: Int2Ext faults
  346. 0x08: Ext2Int faults
  347. 0x10: Bypass faults
  348. DR0_BREAKPOINTS: (counter: all)
  349. DR0 Breakpoint Match (min count: 500)
  350. DR1_BREAKPOINTS: (counter: all)
  351. DR1 Breakpoint Match (min count: 500)
  352. DR2_BREAKPOINTS: (counter: all)
  353. DR2 Breakpoint Match (min count: 500)
  354. DR3_BREAKPOINTS: (counter: all)
  355. DR3 Breakpoint Match (min count: 500)
  356. IBS_OPS_TAGGED: (counter: all)
  357. Tagged IBS Ops (min count: 50000)
  358. Unit masks (default 0x1)
  359. ----------
  360. 0x01: Number of ops tagged by IBS
  361. 0x02: Number of ops tagged by IBS that retired
  362. 0x04: Number of times op could not be tagged by IBS because of previous tagged op that has
  363. not retired
  364. DISPATCH_STALL_FOR_STQ_FULL: (counter: all)
  365. Dispatch Stall for STQ Full (min count: 500)
  366. IBS_FETCH_ALL: (ext: ibs_fetch)
  367. All IBS fetch samples (min count: 50000)
  368. IBS_FETCH_KILLED: (ext: ibs_fetch)
  369. IBS fetch killed (min count: 50000)
  370. IBS_FETCH_ATTEMPTED: (ext: ibs_fetch)
  371. IBS fetch attempted (min count: 50000)
  372. IBS_FETCH_COMPLETED: (ext: ibs_fetch)
  373. IBS fetch completed (min count: 50000)
  374. IBS_FETCH_ABORTED: (ext: ibs_fetch)
  375. IBS fetch aborted (min count: 50000)
  376. IBS_FETCH_ITLB_HITS: (ext: ibs_fetch)
  377. IBS ITLB hit (min count: 50000)
  378. IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_HITS: (ext: ibs_fetch)
  379. IBS L1 ITLB misses (and L2 ITLB hits) (min count: 50000)
  380. IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_MISSES: (ext: ibs_fetch)
  381. IBS L1 L2 ITLB miss (min count: 50000)
  382. IBS_FETCH_ICACHE_MISSES: (ext: ibs_fetch)
  383. IBS instruction cache misses (min count: 50000)
  384. IBS_FETCH_ICACHE_HITS: (ext: ibs_fetch)
  385. IBS instruction cache hit (min count: 50000)
  386. IBS_FETCH_4K_PAGE: (ext: ibs_fetch)
  387. IBS 4K page translation (min count: 50000)
  388. IBS_FETCH_2M_PAGE: (ext: ibs_fetch)
  389. IBS 2M page translation (min count: 50000)
  390. IBS_FETCH_LATENCY: (ext: ibs_fetch)
  391. IBS fetch latency (min count: 50000)
  392. IBS_OP_ALL: (ext: ibs_op)
  393. All IBS op samples (min count: 50000)
  394. Unit masks (default 0x1)
  395. ----------
  396. 0x00: Using IBS OP cycle count mode
  397. 0x01: Using IBS OP dispatch count mode
  398. 0x02: Enable IBS OP Memory Access Log
  399. 0x04: Enable IBS OP Branch Target Address Log
  400. IBS_OP_TAG_TO_RETIRE: (ext: ibs_op)
  401. IBS tag-to-retire cycles (min count: 50000)
  402. Unit masks (default 0x1)
  403. ----------
  404. 0x00: Using IBS OP cycle count mode
  405. 0x01: Using IBS OP dispatch count mode
  406. 0x02: Enable IBS OP Memory Access Log
  407. 0x04: Enable IBS OP Branch Target Address Log
  408. IBS_OP_COMP_TO_RET: (ext: ibs_op)
  409. IBS completion-to-retire cycles (min count: 50000)
  410. Unit masks (default 0x1)
  411. ----------
  412. 0x00: Using IBS OP cycle count mode
  413. 0x01: Using IBS OP dispatch count mode
  414. 0x02: Enable IBS OP Memory Access Log
  415. 0x04: Enable IBS OP Branch Target Address Log
  416. IBS_OP_BRANCH_RETIRED: (ext: ibs_op)
  417. IBS branch op (min count: 50000)
  418. Unit masks (default 0x1)
  419. ----------
  420. 0x00: Using IBS OP cycle count mode
  421. 0x01: Using IBS OP dispatch count mode
  422. 0x02: Enable IBS OP Memory Access Log
  423. 0x04: Enable IBS OP Branch Target Address Log
  424. IBS_OP_MISPREDICTED_BRANCH: (ext: ibs_op)
  425. IBS mispredicted branch op (min count: 50000)
  426. Unit masks (default 0x1)
  427. ----------
  428. 0x00: Using IBS OP cycle count mode
  429. 0x01: Using IBS OP dispatch count mode
  430. 0x02: Enable IBS OP Memory Access Log
  431. 0x04: Enable IBS OP Branch Target Address Log
  432. IBS_OP_TAKEN_BRANCH: (ext: ibs_op)
  433. IBS taken branch op (min count: 50000)
  434. Unit masks (default 0x1)
  435. ----------
  436. 0x00: Using IBS OP cycle count mode
  437. 0x01: Using IBS OP dispatch count mode
  438. 0x02: Enable IBS OP Memory Access Log
  439. 0x04: Enable IBS OP Branch Target Address Log
  440. IBS_OP_MISPREDICTED_BRANCH_TAKEN: (ext: ibs_op)
  441. IBS mispredicted taken branch op (min count: 50000)
  442. Unit masks (default 0x1)
  443. ----------
  444. 0x00: Using IBS OP cycle count mode
  445. 0x01: Using IBS OP dispatch count mode
  446. 0x02: Enable IBS OP Memory Access Log
  447. 0x04: Enable IBS OP Branch Target Address Log
  448. IBS_OP_RETURNS: (ext: ibs_op)
  449. IBS return op (min count: 50000)
  450. Unit masks (default 0x1)
  451. ----------
  452. 0x00: Using IBS OP cycle count mode
  453. 0x01: Using IBS OP dispatch count mode
  454. 0x02: Enable IBS OP Memory Access Log
  455. 0x04: Enable IBS OP Branch Target Address Log
  456. IBS_OP_MISPREDICTED_RETURNS: (ext: ibs_op)
  457. IBS mispredicted return op (min count: 50000)
  458. Unit masks (default 0x1)
  459. ----------
  460. 0x00: Using IBS OP cycle count mode
  461. 0x01: Using IBS OP dispatch count mode
  462. 0x02: Enable IBS OP Memory Access Log
  463. 0x04: Enable IBS OP Branch Target Address Log
  464. IBS_OP_RESYNC: (ext: ibs_op)
  465. IBS resync op (min count: 50000)
  466. Unit masks (default 0x1)
  467. ----------
  468. 0x00: Using IBS OP cycle count mode
  469. 0x01: Using IBS OP dispatch count mode
  470. 0x02: Enable IBS OP Memory Access Log
  471. 0x04: Enable IBS OP Branch Target Address Log
  472. IBS_OP_ALL_LOAD_STORE: (ext: ibs_op)
  473. IBS all load store ops (min count: 50000)
  474. Unit masks (default 0x1)
  475. ----------
  476. 0x00: Using IBS OP cycle count mode
  477. 0x01: Using IBS OP dispatch count mode
  478. 0x02: Enable IBS OP Memory Access Log
  479. 0x04: Enable IBS OP Branch Target Address Log
  480. IBS_OP_LOAD: (ext: ibs_op)
  481. IBS load ops (min count: 50000)
  482. Unit masks (default 0x1)
  483. ----------
  484. 0x00: Using IBS OP cycle count mode
  485. 0x01: Using IBS OP dispatch count mode
  486. 0x02: Enable IBS OP Memory Access Log
  487. 0x04: Enable IBS OP Branch Target Address Log
  488. IBS_OP_STORE: (ext: ibs_op)
  489. IBS store ops (min count: 50000)
  490. Unit masks (default 0x1)
  491. ----------
  492. 0x00: Using IBS OP cycle count mode
  493. 0x01: Using IBS OP dispatch count mode
  494. 0x02: Enable IBS OP Memory Access Log
  495. 0x04: Enable IBS OP Branch Target Address Log
  496. IBS_OP_L1_DTLB_HITS: (ext: ibs_op)
  497. IBS L1 DTLB hit (min count: 50000)
  498. Unit masks (default 0x1)
  499. ----------
  500. 0x00: Using IBS OP cycle count mode
  501. 0x01: Using IBS OP dispatch count mode
  502. 0x02: Enable IBS OP Memory Access Log
  503. 0x04: Enable IBS OP Branch Target Address Log
  504. IBS_OP_L1_DTLB_MISS_L2_DTLB_HIT: (ext: ibs_op)
  505. IBS L1 DTLB misses L2 hits (min count: 50000)
  506. Unit masks (default 0x1)
  507. ----------
  508. 0x00: Using IBS OP cycle count mode
  509. 0x01: Using IBS OP dispatch count mode
  510. 0x02: Enable IBS OP Memory Access Log
  511. 0x04: Enable IBS OP Branch Target Address Log
  512. IBS_OP_L1_L2_DTLB_MISS: (ext: ibs_op)
  513. IBS L1 and L2 DTLB misses (min count: 50000)
  514. Unit masks (default 0x1)
  515. ----------
  516. 0x00: Using IBS OP cycle count mode
  517. 0x01: Using IBS OP dispatch count mode
  518. 0x02: Enable IBS OP Memory Access Log
  519. 0x04: Enable IBS OP Branch Target Address Log
  520. IBS_OP_DATA_CACHE_MISS: (ext: ibs_op)
  521. IBS data cache misses (min count: 50000)
  522. Unit masks (default 0x1)
  523. ----------
  524. 0x00: Using IBS OP cycle count mode
  525. 0x01: Using IBS OP dispatch count mode
  526. 0x02: Enable IBS OP Memory Access Log
  527. 0x04: Enable IBS OP Branch Target Address Log
  528. IBS_OP_DATA_HITS: (ext: ibs_op)
  529. IBS data cache hits (min count: 50000)
  530. Unit masks (default 0x1)
  531. ----------
  532. 0x00: Using IBS OP cycle count mode
  533. 0x01: Using IBS OP dispatch count mode
  534. 0x02: Enable IBS OP Memory Access Log
  535. 0x04: Enable IBS OP Branch Target Address Log
  536. IBS_OP_MISALIGNED_DATA_ACC: (ext: ibs_op)
  537. IBS misaligned data access (min count: 50000)
  538. Unit masks (default 0x1)
  539. ----------
  540. 0x00: Using IBS OP cycle count mode
  541. 0x01: Using IBS OP dispatch count mode
  542. 0x02: Enable IBS OP Memory Access Log
  543. 0x04: Enable IBS OP Branch Target Address Log
  544. IBS_OP_BANK_CONF_LOAD: (ext: ibs_op)
  545. IBS bank conflict on load op (min count: 50000)
  546. Unit masks (default 0x1)
  547. ----------
  548. 0x00: Using IBS OP cycle count mode
  549. 0x01: Using IBS OP dispatch count mode
  550. 0x02: Enable IBS OP Memory Access Log
  551. 0x04: Enable IBS OP Branch Target Address Log
  552. IBS_OP_BANK_CONF_STORE: (ext: ibs_op)
  553. IBS bank conflict on store op (min count: 50000)
  554. Unit masks (default 0x1)
  555. ----------
  556. 0x00: Using IBS OP cycle count mode
  557. 0x01: Using IBS OP dispatch count mode
  558. 0x02: Enable IBS OP Memory Access Log
  559. 0x04: Enable IBS OP Branch Target Address Log
  560. IBS_OP_FORWARD: (ext: ibs_op)
  561. IBS store-to-load forwarded (min count: 50000)
  562. Unit masks (default 0x1)
  563. ----------
  564. 0x00: Using IBS OP cycle count mode
  565. 0x01: Using IBS OP dispatch count mode
  566. 0x02: Enable IBS OP Memory Access Log
  567. 0x04: Enable IBS OP Branch Target Address Log
  568. IBS_OP_CANCELLED: (ext: ibs_op)
  569. IBS store-to-load cancelled (min count: 50000)
  570. Unit masks (default 0x1)
  571. ----------
  572. 0x00: Using IBS OP cycle count mode
  573. 0x01: Using IBS OP dispatch count mode
  574. 0x02: Enable IBS OP Memory Access Log
  575. 0x04: Enable IBS OP Branch Target Address Log
  576. IBS_OP_DCUC_MEM_ACC: (ext: ibs_op)
  577. IBS UC memory access (min count: 50000)
  578. Unit masks (default 0x1)
  579. ----------
  580. 0x00: Using IBS OP cycle count mode
  581. 0x01: Using IBS OP dispatch count mode
  582. 0x02: Enable IBS OP Memory Access Log
  583. 0x04: Enable IBS OP Branch Target Address Log
  584. IBS_OP_DCWC_MEM_ACC: (ext: ibs_op)
  585. IBS WC memory access (min count: 50000)
  586. Unit masks (default 0x1)
  587. ----------
  588. 0x00: Using IBS OP cycle count mode
  589. 0x01: Using IBS OP dispatch count mode
  590. 0x02: Enable IBS OP Memory Access Log
  591. 0x04: Enable IBS OP Branch Target Address Log
  592. IBS_OP_LOCKED: (ext: ibs_op)
  593. IBS locked operation (min count: 50000)
  594. Unit masks (default 0x1)
  595. ----------
  596. 0x00: Using IBS OP cycle count mode
  597. 0x01: Using IBS OP dispatch count mode
  598. 0x02: Enable IBS OP Memory Access Log
  599. 0x04: Enable IBS OP Branch Target Address Log
  600. IBS_OP_MAB_HIT: (ext: ibs_op)
  601. IBS MAB hit (min count: 50000)
  602. Unit masks (default 0x1)
  603. ----------
  604. 0x00: Using IBS OP cycle count mode
  605. 0x01: Using IBS OP dispatch count mode
  606. 0x02: Enable IBS OP Memory Access Log
  607. 0x04: Enable IBS OP Branch Target Address Log
  608. IBS_OP_L1_DTLB_4K: (ext: ibs_op)
  609. IBS L1 DTLB 4K page (min count: 50000)
  610. Unit masks (default 0x1)
  611. ----------
  612. 0x00: Using IBS OP cycle count mode
  613. 0x01: Using IBS OP dispatch count mode
  614. 0x02: Enable IBS OP Memory Access Log
  615. 0x04: Enable IBS OP Branch Target Address Log
  616. IBS_OP_L1_DTLB_2M: (ext: ibs_op)
  617. IBS L1 DTLB 2M page (min count: 50000)
  618. Unit masks (default 0x1)
  619. ----------
  620. 0x00: Using IBS OP cycle count mode
  621. 0x01: Using IBS OP dispatch count mode
  622. 0x02: Enable IBS OP Memory Access Log
  623. 0x04: Enable IBS OP Branch Target Address Log
  624. IBS_OP_L1_DTLB_1G: (ext: ibs_op)
  625. IBS L1 DTLB 1G page (min count: 50000)
  626. Unit masks (default 0x1)
  627. ----------
  628. 0x00: Using IBS OP cycle count mode
  629. 0x01: Using IBS OP dispatch count mode
  630. 0x02: Enable IBS OP Memory Access Log
  631. 0x04: Enable IBS OP Branch Target Address Log
  632. IBS_OP_L2_DTLB_4K: (ext: ibs_op)
  633. IBS L2 DTLB 4K page (min count: 50000)
  634. Unit masks (default 0x1)
  635. ----------
  636. 0x00: Using IBS OP cycle count mode
  637. 0x01: Using IBS OP dispatch count mode
  638. 0x02: Enable IBS OP Memory Access Log
  639. 0x04: Enable IBS OP Branch Target Address Log
  640. IBS_OP_L2_DTLB_2M: (ext: ibs_op)
  641. IBS L2 DTLB 2M page (min count: 50000)
  642. Unit masks (default 0x1)
  643. ----------
  644. 0x00: Using IBS OP cycle count mode
  645. 0x01: Using IBS OP dispatch count mode
  646. 0x02: Enable IBS OP Memory Access Log
  647. 0x04: Enable IBS OP Branch Target Address Log
  648. IBS_OP_L2_DTLB_1G: (ext: ibs_op)
  649. IBS L2 DTLB 1G page (min count: 50000)
  650. Unit masks (default 0x1)
  651. ----------
  652. 0x00: Using IBS OP cycle count mode
  653. 0x01: Using IBS OP dispatch count mode
  654. 0x02: Enable IBS OP Memory Access Log
  655. 0x04: Enable IBS OP Branch Target Address Log
  656. IBS_OP_DC_LOAD_LAT: (ext: ibs_op)
  657. IBS data cache miss load latency (min count: 50000)
  658. Unit masks (default 0x1)
  659. ----------
  660. 0x00: Using IBS OP cycle count mode
  661. 0x01: Using IBS OP dispatch count mode
  662. 0x02: Enable IBS OP Memory Access Log
  663. 0x04: Enable IBS OP Branch Target Address Log
  664. IBS_OP_NB_LOCAL_ONLY: (ext: ibs_op)
  665. IBS Northbridge local (min count: 50000)
  666. Unit masks (default 0x1)
  667. ----------
  668. 0x00: Using IBS OP cycle count mode
  669. 0x01: Using IBS OP dispatch count mode
  670. 0x02: Enable IBS OP Memory Access Log
  671. 0x04: Enable IBS OP Branch Target Address Log
  672. IBS_OP_NB_REMOTE_ONLY: (ext: ibs_op)
  673. IBS Northbridge remote (min count: 50000)
  674. Unit masks (default 0x1)
  675. ----------
  676. 0x00: Using IBS OP cycle count mode
  677. 0x01: Using IBS OP dispatch count mode
  678. 0x02: Enable IBS OP Memory Access Log
  679. 0x04: Enable IBS OP Branch Target Address Log
  680. IBS_OP_NB_LOCAL_L3: (ext: ibs_op)
  681. IBS Northbridge local L3 (min count: 50000)
  682. Unit masks (default 0x1)
  683. ----------
  684. 0x00: Using IBS OP cycle count mode
  685. 0x01: Using IBS OP dispatch count mode
  686. 0x02: Enable IBS OP Memory Access Log
  687. 0x04: Enable IBS OP Branch Target Address Log
  688. IBS_OP_NB_LOCAL_CACHE: (ext: ibs_op)
  689. IBS Northbridge local core L1 or L2 cache (min count: 50000)
  690. Unit masks (default 0x1)
  691. ----------
  692. 0x00: Using IBS OP cycle count mode
  693. 0x01: Using IBS OP dispatch count mode
  694. 0x02: Enable IBS OP Memory Access Log
  695. 0x04: Enable IBS OP Branch Target Address Log
  696. IBS_OP_NB_REMOTE_CACHE: (ext: ibs_op)
  697. IBS Northbridge local core L1, L2, L3 cache (min count: 50000)
  698. Unit masks (default 0x1)
  699. ----------
  700. 0x00: Using IBS OP cycle count mode
  701. 0x01: Using IBS OP dispatch count mode
  702. 0x02: Enable IBS OP Memory Access Log
  703. 0x04: Enable IBS OP Branch Target Address Log
  704. IBS_OP_NB_LOCAL_DRAM: (ext: ibs_op)
  705. IBS Northbridge local DRAM (min count: 50000)
  706. Unit masks (default 0x1)
  707. ----------
  708. 0x00: Using IBS OP cycle count mode
  709. 0x01: Using IBS OP dispatch count mode
  710. 0x02: Enable IBS OP Memory Access Log
  711. 0x04: Enable IBS OP Branch Target Address Log
  712. IBS_OP_NB_REMOTE_DRAM: (ext: ibs_op)
  713. IBS Northbridge remote DRAM (min count: 50000)
  714. Unit masks (default 0x1)
  715. ----------
  716. 0x00: Using IBS OP cycle count mode
  717. 0x01: Using IBS OP dispatch count mode
  718. 0x02: Enable IBS OP Memory Access Log
  719. 0x04: Enable IBS OP Branch Target Address Log
  720. IBS_OP_NB_LOCAL_OTHER: (ext: ibs_op)
  721. IBS Northbridge local APIC MMIO Config PCI (min count: 50000)
  722. Unit masks (default 0x1)
  723. ----------
  724. 0x00: Using IBS OP cycle count mode
  725. 0x01: Using IBS OP dispatch count mode
  726. 0x02: Enable IBS OP Memory Access Log
  727. 0x04: Enable IBS OP Branch Target Address Log
  728. IBS_OP_NB_REMOTE_OTHER: (ext: ibs_op)
  729. IBS Northbridge remote APIC MMIO Config PCI (min count: 50000)
  730. Unit masks (default 0x1)
  731. ----------
  732. 0x00: Using IBS OP cycle count mode
  733. 0x01: Using IBS OP dispatch count mode
  734. 0x02: Enable IBS OP Memory Access Log
  735. 0x04: Enable IBS OP Branch Target Address Log
  736. IBS_OP_NB_CACHE_MODIFIED: (ext: ibs_op)
  737. IBS Northbridge cache modified state (min count: 50000)
  738. Unit masks (default 0x1)
  739. ----------
  740. 0x00: Using IBS OP cycle count mode
  741. 0x01: Using IBS OP dispatch count mode
  742. 0x02: Enable IBS OP Memory Access Log
  743. 0x04: Enable IBS OP Branch Target Address Log
  744. IBS_OP_NB_CACHE_OWNED: (ext: ibs_op)
  745. IBS Northbridge cache owned state (min count: 50000)
  746. Unit masks (default 0x1)
  747. ----------
  748. 0x00: Using IBS OP cycle count mode
  749. 0x01: Using IBS OP dispatch count mode
  750. 0x02: Enable IBS OP Memory Access Log
  751. 0x04: Enable IBS OP Branch Target Address Log
  752. IBS_OP_NB_LOCAL_CACHE_LAT: (ext: ibs_op)
  753. IBS Northbridge local cache latency (min count: 50000)
  754. Unit masks (default 0x1)
  755. ----------
  756. 0x00: Using IBS OP cycle count mode
  757. 0x01: Using IBS OP dispatch count mode
  758. 0x02: Enable IBS OP Memory Access Log
  759. 0x04: Enable IBS OP Branch Target Address Log
  760. IBS_OP_NB_REMOTE_CACHE_LAT: (ext: ibs_op)
  761. IBS Northbridge remote cache latency (min count: 50000)
  762. Unit masks (default 0x1)
  763. ----------
  764. 0x00: Using IBS OP cycle count mode
  765. 0x01: Using IBS OP dispatch count mode
  766. 0x02: Enable IBS OP Memory Access Log
  767. 0x04: Enable IBS OP Branch Target Address Log
  768. [root@tiger src]#
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