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  1. /*
  2.  * This file is part of the coreboot project.
  3.  *
  4.  * Copyright (C) 2006 AMD
  5.  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
  6.  * Copyright (C) 2006 MSI
  7.  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
  8.  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  9.  *
  10.  * This program is free software; you can redistribute it and/or modify
  11.  * it under the terms of the GNU General Public License as published by
  12.  * the Free Software Foundation; either version 2 of the License, or
  13.  * (at your option) any later version.
  14.  *
  15.  * This program is distributed in the hope that it will be useful,
  16.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18.  * GNU General Public License for more details.
  19.  *
  20.  * You should have received a copy of the GNU General Public License
  21.  * along with this program; if not, write to the Free Software
  22.  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23.  */
  24.  
  25. unsigned int get_sbdn(unsigned bus);
  26.  
  27. #include <stdint.h>
  28. #include <string.h>
  29. #include <device/pci_def.h>
  30. #include <arch/io.h>
  31. #include <device/pnp_def.h>
  32. #include <arch/romcc_io.h>
  33. #include <cpu/x86/lapic.h>
  34. #include <pc80/mc146818rtc.h>
  35. #include <console/console.h>
  36. #include <cpu/amd/model_fxx_rev.h>
  37. #include "northbridge/amd/amdk8/raminit.h"
  38. #include "cpu/amd/model_fxx/apic_timer.c"
  39. #include "lib/delay.c"
  40. #include "cpu/x86/lapic/boot_cpu.c"
  41. #include "northbridge/amd/amdk8/reset_test.c"
  42. #include "northbridge/amd/amdk8/early_ht.c"
  43. #include "superio/winbond/w83627ehg/early_serial.c"
  44. #include "superio/winbond/w83627ehg/early_init.c"
  45. #include "southbridge/via/vt8237r/early_smbus.c"
  46. #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
  47. #include "cpu/x86/mtrr/earlymtrr.c"
  48. #include "cpu/x86/bist.h"
  49. #include "northbridge/amd/amdk8/setup_resource_map.c"
  50. #include <spd.h>
  51.  
  52. #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  53. #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
  54. #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
  55.  
  56. static void memreset(int controllers, const struct mem_controller *ctrl) { }
  57. static void activate_spd_rom(const struct mem_controller *ctrl) { }
  58.  
  59.  
  60. static inline int spd_read_byte(unsigned device, unsigned address)
  61. {
  62.         return smbus_read_byte(device, address);
  63. }
  64.  
  65. #include <reset.h>
  66. void soft_reset(void)
  67. {
  68.         uint8_t tmp;
  69.  
  70.         set_bios_reset();
  71.         print_debug("soft reset \n");
  72.  
  73.         /* PCI reset */
  74.         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
  75.         tmp |= 0x01;
  76.         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
  77.  
  78.         while (1) {
  79.                 /* daisy daisy ... */
  80.                 hlt();
  81.         }
  82. }
  83.  
  84. #include "southbridge/via/k8t890/early_car.c"
  85. #include "northbridge/amd/amdk8/amdk8.h"
  86. #include "northbridge/amd/amdk8/incoherent_ht.c"
  87. #include "northbridge/amd/amdk8/coherent_ht.c"
  88. #include "northbridge/amd/amdk8/raminit.c"
  89. #include "lib/generic_sdram.c"
  90. #include "cpu/amd/dualcore/dualcore.c"
  91. #include "cpu/amd/car/post_cache_as_ram.c"
  92. #include "cpu/amd/model_fxx/init_cpus.c"
  93. #include "cpu/amd/model_fxx/fidvid.c"
  94. #include "northbridge/amd/amdk8/resourcemap.c"
  95.  
  96. unsigned int get_sbdn(unsigned bus)
  97. {
  98.         device_t dev;
  99.  
  100.         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  101.                                         PCI_DEVICE_ID_VIA_VT8237A_LPC), bus);
  102.         return (dev >> 15) & 0x1f;
  103. }
  104.  
  105. //static void sio_init(void)
  106. //{
  107. //}
  108.  
  109. void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  110. {
  111.         static const uint16_t spd_addr[] = {
  112.                 // Node 0
  113.                 DIMM0, DIMM2, 0, 0,
  114.                 DIMM1, DIMM3, 0, 0,
  115.                 // Node 1
  116.                 DIMM4, DIMM6, 0, 0,
  117.                 DIMM5, DIMM7, 0, 0,
  118.         };
  119.         unsigned bsp_apicid = 0;
  120.         int needs_reset = 0;
  121.         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
  122.                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  123.  
  124. //      sio_init();
  125. //
  126.     pnp_enter_ext_func_mode(SERIAL_DEV);
  127.     pnp_write_config(SERIAL_DEV, 0x24, 0);
  128.     w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
  129.     pnp_exit_ext_func_mode(SERIAL_DEV);
  130.    
  131. //    w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  132.         print_info("pre: console_init()\n");
  133.         console_init();
  134.         print_info("post: console_init()\n");
  135.         enable_rom_decode();
  136.  
  137.         print_info("now booting... before if...\n");
  138.  
  139.         /* Is this a CPU only reset? Or is this a secondary CPU? */
  140.         if (!cpu_init_detectedx && boot_cpu()) {
  141.                 /* Nothing special needs to be done to find bus 0. */
  142.                 /* Allow the HT devices to be found. */
  143.                 enumerate_ht_chain();
  144.         }
  145.  
  146.         // FIXME why is this executed again? --->
  147. //      sio_init();
  148.  
  149. //      w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  150.         pnp_enter_ext_func_mode(SERIAL_DEV);
  151.         pnp_write_config(SERIAL_DEV, 0x24, 0);
  152.         w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
  153.         pnp_exit_ext_func_mode(SERIAL_DEV);
  154.  
  155.     print_info("done enabling serial\n");
  156.         console_init();
  157.         enable_rom_decode();
  158.         // <--- FIXME why is this executed again?
  159.  
  160.         print_info("now booting... real_main\n");
  161.  
  162.         if (bist == 0)
  163.                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  164.  
  165.         /* Halt if there was a built in self test failure. */
  166.         report_bist_failure(bist);
  167.  
  168.         setup_default_resource_map();
  169.         setup_coherent_ht_domain();
  170.         wait_all_core0_started();
  171.  
  172.         print_info("now booting... Core0 started\n");
  173.  
  174. #if CONFIG_LOGICAL_CPUS==1
  175.         /* It is said that we should start core1 after all core0 launched. */
  176.         start_other_cores();
  177.         wait_all_other_cores_started(bsp_apicid);
  178. #endif
  179.         init_timer();
  180.         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
  181.  
  182.         needs_reset = optimize_link_coherent_ht();
  183.         needs_reset |= optimize_link_incoherent_ht(sysinfo);
  184.         needs_reset |= k8t890_early_setup_ht();
  185.  
  186.         if (needs_reset) {
  187.                 print_debug("ht reset -\n");
  188.                 soft_reset();
  189.         }
  190.  
  191.         /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
  192.         enable_fid_change();
  193.         init_fidvid_bsp(bsp_apicid);
  194.  
  195.         /* Stop the APs so we can start them later in init. */
  196.         allow_all_aps_stop(bsp_apicid);
  197.  
  198.         /* It's the time to set ctrl now. */
  199.         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
  200.  
  201.         enable_smbus();
  202.         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
  203.         post_cache_as_ram();
  204. }
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