Testbench

library ieee;
use ieee.std_logic_1164.all;

entity tb_module_name is
end tb_module_name;

architecture tb of tb_module_name is

    component FSM
        port (
           clk, reset : in STD_LOGIC;
           from_play : in STD_LOGIC;
           from_rx_done_tick : in STD_LOGIC;
           from_delay_done : in STD_LOGIC;
           from_dout : in STD_LOGIC_VECTOR(7 downto 0);
           from_readbus : in STD_LOGIC_VECTOR(7 downto 0);

           --Outputs
           to_addrbus : out STD_LOGIC_VECTOR(7 downto 0);
           to_write_enable : out STD_LOGIC;
           to_delay_on : out STD_LOGIC;
           to_clear_FF : out STD_LOGIC
              );
    end component;

    signal clk, reset : std_logic;
    signal from_play, from_rx_done_tick, from_delay_done   : std_logic; -- module inputs
    signal from_dout, from_readbus : std_logic_vector(7 downto 0); -- module inputs

    --outpust
    signal to_write_enable, to_delay_on, to_clear_FF   : std_logic; -- module outputs
    signal to_addrbus   : std_logic_vector(7 downto 0); -- module outputs

    constant clk_period : time := 10 ns;

begin

    uut : FSM
    port map (clk => clk, reset => reset,
              from_rx_done_tick => from_rx_done_tick, from_play => from_play,
              from_delay_done => from_delay_done, from_dout => from_dout,
              from_readbus => from_readbus, to_write_enable => to_write_enable,
              to_delay_on => to_delay_on, to_clear_ff => to_clear_ff,
              to_addrbus => to_addrbus
              );


clk_process: process
   begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
   end process;

-- Stimuli process
   stim_proc: process
      begin
         from_rx_done_tick <= '1';
         from_delay_done <= '0';
         from_play <= '0';
         from_readbus <= "00000000";
         --reset <= '1';
         wait for clk_period*2;
         --reset <= '0';

         from_readbus<= "11111111";
         from_play <= '1';
         wait for clk_period*50;
         from_delay_done <= '1';
         from_dout <= "01011011";
         from_play <= '1';

      end process ;

end tb;