Bin_TO_7Seg

#predefine Not for later use
def not
port in nin
port out nout
inst n_ot nand nin nin nout
enddef
#
#
#define 4way-OR
def or41
    port in oin4<3:0>
    port out oout4
    net o4net<7:0>

        inst ox4_1 not oin4<0> o4net<0>
        inst ox4_2 not oin4<1> o4net<1>
        inst ox4_3 not oin4<2> o4net<2>
        inst ox4_4 not oin4<3> o4net<3>
        inst ox4_5 nand o4net<0> o4net<1> o4net<4>
        inst ox4_6 nand o4net<2> o4net<3> o4net<5>
        inst ox4_7 not o4net<4> o4net<6>
        inst ox4_8 not o4net<6> o4net<7>
        inst ox4_9 nand o4net<6> o4net<7> oout4
        inst o4in io_out8 false,false,false,false,oin4<3:0>
        inst o4out io_out oout4
enddef
#
#
#define 3way-OR
def OR31
    port in oin3<2:0>
    port out oout3
    net o3net<4:0>

        inst ox3_1 not oin3<0> o3net<0>
        inst ox3_2 not oin3<1> o3net<1>
        inst ox3_3 not oin3<2> o3net<2>
        inst ox3_4 nand o3net<0> o3net<1> o3net<3>
        inst ox3_5 not o3net<3> o3net<4>
        inst ox3_6 nand o3net<2> o3net<4> oout3
        inst o3in io_out8 false,false,false,false,false,oin3<2:0>
        inst o3out io_out oout3
enddef
#
#
#peww..... OR's defined....
#now the AND's
#define 4way-AND
def and4
    port in ain41
    port in ain42
    port in ain43
    port in ain44
    port out aout4
    net a41
    net a42
    net a43
    net a44
    net a45

        inst ax4_1 nand ain41 ain42 a41
        inst ax4_2 nand ain43 ain44 a42
        inst ax4_3 not a41 a43
        inst ax4_4 not a42 a44
        inst ax4_5 nand a43 a44 a45
        inst ax4_6 not a45 aout4

enddef
#
#
#define 3way-AND
def and3
    port in ain31
    port in ain32
    port in ain33
    port out aout3
    net a31
    net a32
    net a33

        inst ax3_1 nand ain31 ain32 a31
        inst ax3_2 not a31 a32
        inst ax3_3 nand a32 ain33 a33
        inst ax3_4 not a33 aout3

enddef
#
#finally the (E/A)ND of predefines....
#define AND
def AND
    port in ain21
    port in ain22
    port out aout2
    net a21

        inst ax2_1 nand ain21 ain22 a21
        inst ax2_2 not a21 aout2

enddef
#
#Now the fun-part....
#
def BIN_TO_7SEG
    port in BIN<3:0>
    port out a
    port out b
    port out c
    port out d
    port out e
    port out f
    port out g
#define net's for segments separately
    net na<3:0>
    net nb<3:0>
    net nc<2:0>
    net nd<3:0>
    net ne<2:0>
    net nf<3:0>
    net ng<2:0>
#define nets for Inverted BIN's
    net nbn0
    net nbn1
    net nbn2
    net nbn3
#Net for Segments ( they need to get inverted before send to port )
    net notA
    net notb
    net notc
    net notd
    net note
    net notf
    net notg

#predefine NOT-BIN's
        inst bnot0 not bin<0> nbn0
        inst bnot1 not bin<1> nbn1
        inst bnot2 not bin<2> nbn2
        inst bnot3 not bin<3> nbn3
#dont believe it, but i rewrote this section about 10 times ...
#define Segment notA
        inst a1 and4 bin<0> nbn1 nbn2 nbn3 na<0>
        inst a2 and4 nbn0 nbn1 bin<2> nbn3 na<1>
        inst a3 and4 bin<0> bin<1> nbn2 bin<3> na<2>
        inst a4 and4 bin<0> nbn1 bin<2> bin<3> na<3>
        inst NOT_A_OR OR41 na<3:0> notA

#define Segment notB
        inst b1 and4 bin<0> nbn1 bin<2> nbn3 nb<0>
        inst b2 and3 nbn0 bin<1> bin<2> nb<1>
        inst b3 and3 bin<0> bin<1> bin<3> nb<2>
        inst b4 and3 nbn0 bin<2> bin<3> nb<3>
        inst NOT_B_OR OR41 nb<3:0> notB

#define Segment notC
        inst c1 and4 nbn0 bin<1> nbn2 nbn3 nc<0>
        inst c2 and3 nbn0 bin<2> bin<3> nc<1>
        inst c3 and3 bin<1> bin<2> bin<3> nc<2>
        inst NOT_C_OR OR31 nc<2:0> notC

#define Segment notD
        inst d1 and4 bin<0> nbn1 nbn2 nbn3 nd<0>
        inst d2 and4 nbn0 nbn1 bin<2> nbn3 nd<1>
        inst d3 and3 bin<0> bin<1> bin<2> nd<2>
        inst d4 and4 nbn0 bin<1> nbn2 bin<3> nd<3>
        inst NOT_D_OR OR41 nd<3:0> notD

#define Segment notE
        inst e1 and bin<0> nbn3 ne<0>
        inst e2 and3 bin<0> nbn1 nbn2 ne<1>
        inst e3 and3 nbn1 bin<2> nbn3 ne<2>
        inst NOT_E_OR OR31 ne<2:0> notE

#define Segment notF
        inst f1 and3 bin<0> nbn2 nbn3 nf<0>
        inst f2 and3 bin<2> nbn2 nbn3 nf<1>
        inst f3 and3 bin<0> bin<1> nbn3 nf<2>
        inst NOT_F_OR OR31 nf<2:0> notF

#define Segment notG
        inst g1 and3 nbn1 nbn2 nbn3 ng<0>
        inst g2 and4 bin<0> bin<1> bin<2> nbn3 ng<1>
        inst g3 and4 nbn0 nbn1 bin<2> bin<3> ng<2>
        inst NOT_G_OR OR31 ng<2:0> notG

#invert Segments for Display-use
        inst n1 not notA A
        inst n2 not notB B
        inst n3 not notC C
        inst n4 not notD D
        inst n5 not notE E
        inst n6 not notF F
        inst n7 not notG G
#Done -.- finally
Enddef
#
#
# Test-Preload
DEF TOP
  NET BIN<3:0>
  NET A
  NET B
  NET C
  NET D
  NET E
  NET F
  NET G
  INST BIN_TO_7SEG BIN_TO_7SEG BIN<3:0> A B C D E F G
  INST TEST BIN_TO_7SEG_TEST BIN<3:0> A B C D E F G
  INST OUTBIN IO_OUT8 false,false,false,false,BIN<3:0>
  INST OUT7SEG IO_OUT7SEG A B C D E F G
ENDDEF