----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:45:46 12/01/2016
-- Design Name:
-- Module Name:    sevSegment - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sevSegment is
port (
	clk : in std_logic;
	value : in std_logic_vector(15 downto 0);
	enable : out std_logic_vector(3 downto 0); -- vector?
	sevenSeg : out std_logic_vector(7 downto 0)

);
end sevSegment;

architecture Behavioral of sevSegment is
constant ZERO : std_logic_vector(7 downto 0) := "00000011";
constant ONE : std_logic_vector(7 downto 0) := "10011111";
constant TWO : std_logic_vector(7 downto 0) := "00100101";
constant THREE : std_logic_vector(7 downto 0) := "00001101";
constant FOUR : std_logic_vector(7 downto 0) := "10011001";
constant FIVE : std_logic_vector(7 downto 0) := "01001001";
constant SIX : std_logic_vector(7 downto 0) := "01000001";
constant SEVEN : std_logic_vector(7 downto 0) := "00011111";
constant EIGHT : std_logic_vector(7 downto 0) := "00000001";
constant NINE : std_logic_vector(7 downto 0) := "00001001";
constant A: std_logic_vector(7 downto 0) := "00010001";
constant B : std_logic_vector(7 downto 0) := "11000001";
constant C : std_logic_vector(7 downto 0) := "01100011";
constant D : std_logic_vector(7 downto 0) := "10000101";
constant E : std_logic_vector(7 downto 0) := "01100001";
constant F : std_logic_vector(7 downto 0) := "01110001";


signal sigenable : std_logic_vector(3 downto 0) :="1111";
signal sigsevenSeg : std_logic_vector(7 downto 0) :="11111111";
signal valueSlice : std_logic_vector(3 downto 0) :="0000";
 begin

	process (clk,value)
	 variable x : integer range 1 to 4 := 1;
    begin

		if (clk'event and clk = '1') then
				valueSlice <= value( (x*4-1) downto ((x-1)*4));
				case valueSlice is
					when "0000" => sigsevenSeg <= ZERO;
					when "0001" => sigsevenSeg <= ONE;
					when "0010" => sigsevenSeg <= TWO;
					when "0011" => sigsevenSeg <= THREE;
					when "0100" => sigsevenSeg <= FOUR;
					when "0101" => sigsevenSeg <= FIVE;
					when "0110" => sigsevenSeg <= SIX;
					when "0111" => sigsevenSeg <= SEVEN;
					when "1000" => sigsevenSeg <= EIGHT;
					when "1001" => sigsevenSeg <= NINE;
					when "1010" => sigsevenSeg <= A;
					when "1011" => sigsevenSeg <= B;
					when "1100" => sigsevenSeg <= C;
					when "1101" => sigsevenSeg <= D;
					when "1110" => sigsevenSeg <= E;
					when "1111" => sigsevenSeg <= F;
					when others => null;
				end case;

				case x is
					when 1 => sigenable <= "1110"; -- AN0
					when 2 => sigenable <= "1101"; -- AN1
					when 3 => sigenable <= "1011"; -- AN2
					when 4 => sigenable <= "0111"; -- AN3
				end case;

				if (x = 4) then
					x := 1;
				else
					x := x+1;
				end if;
			end if;
	enable <= sigenable;
	sevenseg <= sigsevenseg;

	end process;
end Behavioral;