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  1. /*
  2. * Allwinner Technology CO., Ltd. sun50iw1p1 platform
  3. *
  4. * fpga support
  5. * modify base on juno.dts
  6. */
  7. /* kernel used */
  8. /memreserve/ 0x45000000 0x00200000; /* sun50iw1p1.dtb range : [0x45000000~0x45200000], size = 2M */
  9. /memreserve/ 0x41010000 0x00010000; /* sys_config.fex range : [0x41010000~0x41020000], size = 64K */
  10. /memreserve/ 0x41020000 0x00000800; /* super standby range : [0x41020000~0x41020800], size = 2K */
  11. /* tf used */
  12. /memreserve/ 0x40100000 0x00004000; /* arisc dram code space range: [0x40100000~0x40104000], size = 16K */
  13. /memreserve/ 0x40104000 0x00001000; /* arisc para cfg range : [0x40104000~0x40105000], size = 4K */
  14. /memreserve/ 0x40105000 0x00001000; /* arisc message pool range : [0x40105000~0x40106000], size = 4K */
  15.  
  16. #include <dt-bindings/interrupt-controller/arm-gic.h>
  17. #include <dt-bindings/gpio/gpio.h>
  18. #include "sun50iw1p1-clk.dtsi"
  19. #include "sun50iw1p1-pinctrl.dtsi"
  20. / {
  21. model = "sun50iw1p1";
  22. compatible = "arm,sun50iw1p1", "arm,sun50iw1p1";
  23. interrupt-parent = <&gic>;
  24. #address-cells = <2>;
  25. #size-cells = <2>;
  26.  
  27. aliases {
  28. serial0 = &uart0;
  29. serial1 = &uart1;
  30. serial2 = &uart2;
  31. serial3 = &uart3;
  32. serial4 = &uart4;
  33. twi0 = &twi0;
  34. twi1 = &twi1;
  35. twi2 = &twi2;
  36. spi0 = &spi0;
  37. spi1 = &spi1;
  38. global_timer0 = &soc_timer0;
  39. cci0 = &csi_cci0;
  40. csi_res0 = &csi_res0;
  41. vfe0 = &csi0;
  42. mmc0 = &sdc0;
  43. mmc2 = &sdc2;
  44. nand0 =&nand0;
  45. disp = &disp;
  46. lcd0 = &lcd0;
  47. hdmi = &hdmi;
  48. pwm = &pwm;
  49. boot_disp = &boot_disp;
  50. };
  51.  
  52. chosen {
  53. bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  54. linux,initrd-start = <0x0 0x0>;
  55. linux,initrd-end = <0x0 0x0>;
  56. };
  57.  
  58. cpus {
  59. #address-cells = <2>;
  60. #size-cells = <0>;
  61.  
  62. cpu@0 {
  63. device_type = "cpu";
  64. compatible = "arm,cortex-a53","arm,armv8";
  65. reg = <0x0 0x0>;
  66. enable-method = "psci";
  67. cpufreq_tbl = < 480000
  68. 600000
  69. 720000
  70. 816000
  71. 1008000
  72. 1104000
  73. 1152000
  74. 1200000
  75. 1344000>;
  76. clock-latency = <2000000>;
  77. clock-frequency = <1008000000>;
  78. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  79. };
  80. cpu@1 {
  81. device_type = "cpu";
  82. compatible = "arm,cortex-a53","arm,armv8";
  83. reg = <0x0 0x1>;
  84. enable-method = "psci";
  85. clock-frequency = <1008000000>;
  86. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  87. };
  88. cpu@2 {
  89. device_type = "cpu";
  90. compatible = "arm,cortex-a53","arm,armv8";
  91. reg = <0x0 0x2>;
  92. enable-method = "psci";
  93. clock-frequency = <1008000000>;
  94. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  95. };
  96. cpu@3 {
  97. device_type = "cpu";
  98. compatible = "arm,cortex-a53","arm,armv8";
  99. reg = <0x0 0x3>;
  100. enable-method = "psci";
  101. clock-frequency = <1008000000>;
  102. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  103. };
  104. idle-states {
  105. entry-method = "arm,psci";
  106.  
  107. CPU_SLEEP_0: cpu-sleep-0 {
  108. compatible = "arm,idle-state";
  109. arm,psci-suspend-param = <0x0010000>;
  110. entry-latency-us = <40>;
  111. exit-latency-us = <100>;
  112. min-residency-us = <150>;
  113. };
  114.  
  115. CLUSTER_SLEEP_0: cluster-sleep-0 {
  116. compatible = "arm,idle-state";
  117. arm,psci-suspend-param = <0x1010000>;
  118. entry-latency-us = <500>;
  119. exit-latency-us = <1000>;
  120. min-residency-us = <2500>;
  121. };
  122.  
  123. SYS_SLEEP_0: sys-sleep-0 {
  124. compatible = "arm,idle-state";
  125. arm,psci-suspend-param = <0x2010000>;
  126. entry-latency-us = <1000>;
  127. exit-latency-us = <2000>;
  128. min-residency-us = <4500>;
  129. };
  130. };
  131. };
  132.  
  133. psci {
  134. compatible = "arm,psci-0.2";
  135. method = "smc";
  136. psci_version = <0x84000000>;
  137. cpu_suspend = <0xc4000001>;
  138. cpu_off = <0x84000002>;
  139. cpu_on = <0xc4000003>;
  140. affinity_info = <0xc4000004>;
  141. migrate = <0xc4000005>;
  142. migrate_info_type = <0x84000006>;
  143. migrate_info_up_cpu = <0xc4000007>;
  144. system_off = <0x84000008>;
  145. system_reset = <0x84000009>;
  146.  
  147. };
  148. n_brom {
  149. compatible = "allwinner,n-brom";
  150. reg = <0x0 0x0 0x0 0xc000>;
  151. };
  152.  
  153. s_brom {
  154. compatible = "allwinner,s-brom";
  155. reg = <0x0 0x0 0x0 0x10000>;
  156. };
  157.  
  158. sram_a1 {
  159. compatible = "allwinner,sram_a1";
  160. reg = <0x0 0x00010000 0x0 0x8000>;
  161. };
  162.  
  163. sram_a2 {
  164. compatible = "allwinner,sram_a2";
  165. reg = <0x0 0x00040000 0x0 0x14000>;
  166. };
  167.  
  168. prcm {
  169. compatible = "allwinner,prcm";
  170. reg = <0x0 0x01f01400 0x0 0x400>;
  171. };
  172.  
  173. cpuscfg {
  174. compatible = "allwinner,cpuscfg";
  175. reg = <0x0 0x01f01c00 0x0 0x400>;
  176. };
  177.  
  178. ion {
  179. compatible = "allwinner,sunxi-ion";
  180. /*types is list here:
  181. ION_HEAP_TYPE_SYSTEM = 0,
  182. ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
  183. ION_HEAP_TYPE_CARVEOUT = 2,
  184. ION_HEAP_TYPE_CHUNK = 3,
  185. ION_HEAP_TYPE_DMA = 4
  186. **/
  187. system_contig{
  188. type = <1>;
  189. name = "system_contig";
  190. };
  191. cma{
  192. type = <4>;
  193. name = "cma";
  194. };
  195. system{
  196. type = <0>;
  197. name = "system";
  198. };
  199. };
  200.  
  201. dram: dram {
  202. compatible = "allwinner,dram";
  203. clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>;
  204. clock-names = "pll_ddr0", "pll_ddr1";
  205. dram_clk = <672>;
  206. dram_type = <3>;
  207. dram_zq = <0x003F3FDD>;
  208. dram_odt_en = <1>;
  209. dram_para1 = <0x10f41000>;
  210. dram_para2 = <0x00001200>;
  211. dram_mr0 = <0x1A50>;
  212. dram_mr1 = <0x40>;
  213. dram_mr2 = <0x10>;
  214. dram_mr3 = <0>;
  215. dram_tpr0 = <0x04E214EA>;
  216. dram_tpr1 = <0x004214AD>;
  217. dram_tpr2 = <0x10A75030>;
  218. dram_tpr3 = <0>;
  219. dram_tpr4 = <0>;
  220. dram_tpr5 = <0>;
  221. dram_tpr6 = <0>;
  222. dram_tpr7 = <0>;
  223. dram_tpr8 = <0>;
  224. dram_tpr9 = <0>;
  225. dram_tpr10 = <0>;
  226. dram_tpr11 = <0>;
  227. dram_tpr12 = <168>;
  228. dram_tpr13 = <0x823>;
  229. };
  230.  
  231. memory@40000000 {
  232. device_type = "memory";
  233. reg = <0x00000000 0x40000000 0x00000000 0x40000000>;
  234. };
  235.  
  236. gic: interrupt-controller@1c81000 {
  237. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  238. #interrupt-cells = <3>;
  239. #address-cells = <0>;
  240. device_type = "gic";
  241. interrupt-controller;
  242. reg = <0x0 0x01c81000 0 0x1000>, /* GIC Dist */
  243. <0x0 0x01c82000 0 0x2000>, /* GIC CPU */
  244. <0x0 0x01c84000 0 0x2000>, /* GIC VCPU Control */
  245. <0x0 0x01c86000 0 0x2000>; /* GIC VCPU */
  246. interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
  247. };
  248.  
  249. chipid: sunxi-chipid@1c14200 {
  250. compatible = "sunxi,sun50i-chipid";
  251. device_type = "chipid";
  252. reg = <0x0 0x01c14200 0 0x0400>; /* chipid */
  253. };
  254.  
  255. timer {
  256. compatible = "arm,armv8-timer";
  257. interrupts = <GIC_PPI 13 0xff01>, /* Secure Phys IRQ */
  258. <GIC_PPI 14 0xff01>, /* Non-secure Phys IRQ */
  259. <GIC_PPI 11 0xff01>, /* Virt IRQ */
  260. <GIC_PPI 10 0xff01>; /* Hyp IRQ */
  261. clock-frequency = <24000000>;
  262. };
  263.  
  264. pmu {
  265. compatible = "arm,armv8-pmuv3";
  266. interrupts = <GIC_SPI 120 4>,
  267. <GIC_SPI 121 4>,
  268. <GIC_SPI 122 4>,
  269. <GIC_SPI 123 4>;
  270. };
  271.  
  272. dvfs_table: dvfs_table {
  273. compatible = "allwinner,dvfs_table";
  274. max_freq = <1200000000>;
  275. min_freq = <480000000>;
  276. lv_count = <8>;
  277. lv1_freq = <1200000000>;
  278. lv1_volt = <1300>;
  279. lv2_freq = <1008000000>;
  280. lv2_volt = <1200>;
  281. lv3_freq = <816000000>;
  282. lv3_volt = <1100>;
  283. lv4_freq = <648000000>;
  284. lv4_volt = <1040>;
  285. lv5_freq = <0>;
  286. lv5_volt = <1040>;
  287. lv6_freq = <0>;
  288. lv6_volt = <1040>;
  289. lv7_freq = <0>;
  290. lv7_volt = <1040>;
  291. lv8_freq = <0>;
  292. lv8_volt = <1040>;
  293. };
  294.  
  295. dramfreq {
  296. compatible = "allwinner,sunxi-dramfreq";
  297. reg = <0x0 0x01c62000 0x0 0x1000>,
  298. <0x0 0x01c63000 0x0 0x1000>,
  299. <0x0 0x01c20000 0x0 0x800>;
  300. clocks = <&clk_pll_ddr0>,<&clk_pll_ddr1>,<&clk_ahb1>;
  301. status = "okay";
  302. };
  303.  
  304. uboot: uboot {
  305. };
  306.  
  307. gpu_mali400_0: gpu@0x01c40000 {
  308. compatible = "arm,mali-400", "arm,mali-utgard";
  309. reg = <0x0 0x01c40000 0x0 0x10000>;
  310. interrupts = <GIC_SPI 97 4>, <GIC_SPI 98 4>, <GIC_SPI 99 4>, <GIC_SPI 100 4>, <GIC_SPI 102 4>, <GIC_SPI 103 4>;
  311. interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
  312. clocks = <&clk_pll_gpu>, <&clk_gpu>;
  313. };
  314.  
  315. soc: soc@01c00000 {
  316. compatible = "simple-bus";
  317. #address-cells = <2>;
  318. #size-cells = <2>;
  319. ranges;
  320. device_type = "soc";
  321. dma0:dma-controller@01c02000 {
  322. compatible = "allwinner,sun50i-dma";
  323. reg = <0x0 0x01c02000 0x0 0x1000>;
  324. interrupts = <0 50 4>;
  325. clocks = <&clk_dma>;
  326. #dma-cells = <1>;
  327. };
  328.  
  329. mbus0:mbus-controller@01c62000 {
  330. compatible = "allwinner,sun50i-mbus";
  331. reg = <0x0 0x01c62000 0x0 0x110>;
  332. #mbus-cells = <1>;
  333. };
  334.  
  335. arisc {
  336. compatible = "allwinner,sunxi-arisc";
  337. #address-cells = <2>;
  338. #size-cells = <2>;
  339. clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>;
  340. clock-names = "losc", "iosc", "hosc", "pll_periph0";
  341. powchk_used = <0x0>;
  342. power_reg = <0x02309621>;
  343. system_power = <50>;
  344. };
  345.  
  346. arisc_space {
  347. compatible = "allwinner,arisc_space";
  348. /* num dst offset size */
  349. space1 = <0x00040000 0x00000000 0x00014000>; /* srama2 code space */
  350. space2 = <0x40100000 0x00018000 0x00004000>; /* dram code space */
  351. space3 = <0x40104000 0x00000000 0x00001000>; /* para space */
  352. space4 = <0x40105000 0x00000000 0x00001000>; /* msgpool space */
  353. };
  354.  
  355. standby_space {
  356. compatible = "allwinner,standby_space";
  357. /* num dst offset size */
  358. space1 = <0x41020000 0x00000000 0x00000800>; /* super standby para space */
  359. };
  360.  
  361. msgbox: msgbox@1c17000 {
  362. compatible = "allwinner,msgbox";
  363. clocks = <&clk_msgbox>;
  364. clock-names = "clk_msgbox";
  365. reg = <0x0 0x01c17000 0x0 0x1000>;
  366. interrupts = <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
  367. status = "okay";
  368. };
  369.  
  370. hwspinlock: hwspinlock@1c18000 {
  371. compatible = "allwinner,sunxi-hwspinlock";
  372. clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>;
  373. clock-names = "clk_hwspinlock_rst" , "clk_hwspinlock_bus";
  374. reg = <0x0 0x01c18000 0x0 0x1000>;
  375. status = "okay";
  376. num-locks = <8>; /* the number hwspinlock we needed, max 32 */
  377. };
  378.  
  379. s_cir0: s_cir@1f02000 {
  380. compatible = "allwinner,s_cir";
  381. reg = <0x0 0x01f02000 0x0 0x400>;
  382. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&s_cir0_pins_a>;
  385. clocks = <&clk_hosc>,<&clk_cpurcir>;
  386. supply = "vcc-pl";
  387. ir_power_key_code = <0>;
  388. ir_addr_code = <0>;
  389. status = "okay";
  390. };
  391.  
  392. s_uart0: s_uart@1f02800 {
  393. compatible = "allwinner,s_uart";
  394. reg = <0x0 0x01f02800 0x0 0x400>;
  395. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  396. pinctrl-names = "default";
  397. pinctrl-0 = <&s_uart0_pins_a>;
  398. status = "okay";
  399. };
  400.  
  401. s_rsb0: s_rsb@1f03400 {
  402. compatible = "allwinner,s_rsb";
  403. reg = <0x0 0x01f03400 0x0 0x400>;
  404. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  405. pinctrl-names = "default";
  406. pinctrl-0 = <&s_rsb0_pins_a>;
  407. status = "okay";
  408. };
  409.  
  410. s_jtag0: s_jtag0 {
  411. compatible = "allwinner,s_jtag";
  412. pinctrl-names = "default";
  413. pinctrl-0 = <&s_jtag0_pins_a>;
  414. status = "disable";
  415. };
  416.  
  417. soc_timer0: timer@1c20c00 {
  418. compatible = "allwinner,sunxi-timer";
  419. device_type = "timer";
  420. reg = <0x0 0x01c20c00 0x0 0x90>;
  421. interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
  422. clock-frequency = <24000000>;
  423. timer-prescale = <16>;
  424. };
  425.  
  426. rtc: rtc@01f00000 {
  427. compatible = "allwinner,sun50i-rtc";
  428. device_type = "rtc";
  429. reg = <0x0 0x1f00000 0x0 0x218>;
  430. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  431. gpr_offset = <0x100>;
  432. gpr_len = <4>;
  433. };
  434.  
  435. ve@01c0e000 {
  436. compatible = "allwinner,sunxi-cedar-ve";
  437. reg = <0x0 0x01c0e000 0x0 0x1000>,
  438. <0x0 0x01c00000 0x0 0x10>,
  439. <0x0 0x01c20000 0x0 0x800>;
  440. interrupts = <GIC_SPI 58 4>;
  441. clocks = <&clk_pll_ve>,
  442. <&clk_ve>;
  443.  
  444. };
  445.  
  446. uart0: uart@01c28000 {
  447. compatible = "allwinner,sun50i-uart";
  448. device_type = "uart0";
  449. reg = <0x0 0x01c28000 0x0 0x400>;
  450. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  451. clocks = <&clk_uart0>;
  452. pinctrl-names = "default", "sleep";
  453. pinctrl-0 = <&uart0_pins_a>;
  454. pinctrl-1 = <&uart0_pins_b>;
  455. uart0_port = <0>;
  456. uart0_type = <2>;
  457. status = "disabled";
  458. };
  459.  
  460. uart1: uart@01c28400 {
  461. compatible = "allwinner,sun50i-uart";
  462. device_type = "uart1";
  463. reg = <0x0 0x01c28400 0x0 0x400>;
  464. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  465. clocks = <&clk_uart1>;
  466. pinctrl-names = "default", "sleep";
  467. pinctrl-0 = <&uart1_pins_a>;
  468. pinctrl-1 = <&uart1_pins_b>;
  469. uart1_port = <1>;
  470. uart1_type = <4>;
  471. status = "okay";
  472. };
  473.  
  474. uart2: uart@01c28800 {
  475. compatible = "allwinner,sun50i-uart";
  476. device_type = "uart2";
  477. reg = <0x0 0x01c28800 0x0 0x400>;
  478. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  479. clocks = <&clk_uart2>;
  480. pinctrl-names = "default", "sleep";
  481. pinctrl-0 = <&uart2_pins_a>;
  482. pinctrl-1 = <&uart2_pins_b>;
  483. uart2_port = <2>;
  484. uart2_type = <4>;
  485. status = "disabled";
  486. };
  487.  
  488. uart3: uart@01c28c00 {
  489. compatible = "allwinner,sun50i-uart";
  490. device_type = "uart3";
  491. reg = <0x0 0x01c28c00 0x0 0x400>;
  492. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  493. clocks = <&clk_uart3>;
  494. pinctrl-names = "default", "sleep";
  495. pinctrl-0 = <&uart3_pins_a>;
  496. pinctrl-1 = <&uart3_pins_b>;
  497. uart3_port = <3>;
  498. uart3_type = <4>;
  499. status = "disabled";
  500. };
  501.  
  502. uart4: uart@01c29000 {
  503. compatible = "allwinner,sun50i-uart";
  504. device_type = "uart4";
  505. reg = <0x0 0x01c29000 0x0 0x400>;
  506. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  507. clocks = <&clk_uart4>;
  508. pinctrl-names = "default", "sleep";
  509. pinctrl-0 = <&uart4_pins_a>;
  510. pinctrl-1 = <&uart4_pins_b>;
  511. uart4_port = <4>;
  512. uart4_type = <4>;
  513. status = "disabled";
  514. };
  515.  
  516. twi0: twi@0x01c2ac00{
  517. #address-cells = <1>;
  518. #size-cells = <0>;
  519. compatible = "allwinner,sun50i-twi";
  520. device_type = "twi0";
  521. reg = <0x0 0x01c2ac00 0x0 0x400>;
  522. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  523. clocks = <&clk_twi0>;
  524. clock-frequency = <400000>;
  525. pinctrl-names = "default", "sleep";
  526. pinctrl-0 = <&twi0_pins_a>;
  527. pinctrl-1 = <&twi0_pins_b>;
  528. status = "disabled";
  529. };
  530.  
  531. twi1: twi@0x01c2b000{
  532. #address-cells = <1>;
  533. #size-cells = <0>;
  534. compatible = "allwinner,sun50i-twi";
  535. device_type = "twi1";
  536. reg = <0x0 0x01c2b000 0x0 0x400>;
  537. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  538. clocks = <&clk_twi1>;
  539. clock-frequency = <200000>;
  540. pinctrl-names = "default", "sleep";
  541. pinctrl-0 = <&twi1_pins_a>;
  542. pinctrl-1 = <&twi1_pins_b>;
  543. status = "disabled";
  544. };
  545.  
  546. twi2: twi@0x01c2b400{
  547. #address-cells = <1>;
  548. #size-cells = <0>;
  549. compatible = "allwinner,sun50i-twi";
  550. device_type = "twi2";
  551. reg = <0x0 0x01c2b400 0x0 0x400>;
  552. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  553. clocks = <&clk_twi2>;
  554. clock-frequency = <200000>;
  555. pinctrl-names = "default", "sleep";
  556. pinctrl-0 = <&twi2_pins_a>;
  557. pinctrl-1 = <&twi2_pins_b>;
  558. status = "disabled";
  559. };
  560.  
  561. usbc0:usbc0@0 {
  562. device_type = "usbc0";
  563. compatible = "allwinner,sun50i-otg-manager";
  564. usb_port_type = <2>;
  565. usb_detect_type = <1>;
  566. usb_id_gpio = <&pio PH 9 0 1 1 1>;
  567. usb_det_vbus_gpio = "axp_ctrl";
  568. usb_drv_vbus_gpio = <&axp_pio PP 3 1 1 1 1>;
  569. usb_host_init_state = <0>;
  570. usb_regulator_io = "nocare";
  571. usb_wakeup_suspend = <0>;
  572. usb_luns = <3>;
  573. usb_serial_unique = <0>;
  574. usb_serial_number = "20080411";
  575. rndis_wceis = <1>;
  576. status = "okay";
  577. };
  578.  
  579. udc:udc-controller@0x01c19000 {
  580. compatible = "allwinner,sun50i-udc";
  581. reg = <0x0 0x01c19000 0x0 0x1000>, /*udc base*/
  582. <0x0 0x01c00000 0x0 0x100>; /*sram base*/
  583. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  584. clocks = <&clk_usbphy0>, <&clk_usbotg>;
  585. status = "okay";
  586. };
  587.  
  588. ehci0:ehci0-controller@0x01c1a000 {
  589. compatible = "allwinner,sun50i-ehci0";
  590. reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/
  591. <0x0 0x01c00000 0x0 0x100>, /*sram base*/
  592. <0x0 0x01c19000 0x0 0x1000>; /*otg base*/
  593. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  594. clocks = <&clk_usbphy0>, <&clk_usbehci0>;
  595. hci_ctrl_no = <0>;
  596. status = "okay";
  597. };
  598.  
  599. ohci0:ohci0-controller@0x01c1a400 {
  600. compatible = "allwinner,sun50i-ohci0";
  601. reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/
  602. <0x0 0x01c00000 0x0 0x100>, /*sram base*/
  603. <0x0 0x01c19000 0x0 0x1000>; /*otg base*/
  604. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  605. clocks = <&clk_usbphy0>, <&clk_usbohci0>;
  606. hci_ctrl_no = <0>;
  607. status = "okay";
  608. };
  609.  
  610. usbc1:usbc1@0 {
  611. device_type = "usbc1";
  612. usb_drv_vbus_gpio = <&pio PB 6 1 1 1 1>;
  613. usb_host_init_state = <1>;
  614. usb_regulator_io = "nocare";
  615. usb_wakeup_suspend = <0>;
  616. /* HISC device */
  617. usb_hsic_used = <0>;
  618. usb_hsic_regulator_io = "vcc-hsic-12";
  619. /*Marvell 4G HSIC */
  620. usb_hsic_ctrl = <0>;
  621. usb_hsic_rdy_gpio;
  622. /* SMSC usb3503 HSIC HUB */
  623. usb_hsic_usb3503_flag = <0>;
  624. usb_hsic_hub_connect_gpio;
  625. usb_hsic_int_n_gpio;
  626. usb_hsic_reset_n_gpio;
  627. status = "okay";
  628. };
  629.  
  630. ehci1:ehci1-controller@0x01c1b000 {
  631. compatible = "allwinner,sun50i-ehci1";
  632. reg = <0x0 0x01c1b000 0x0 0xFFF>,/*hci1 base*/
  633. <0x0 0x01c00000 0x0 0x100>, /*sram base*/
  634. <0x0 0x01c19000 0x0 0x1000>; /*otg base*/
  635. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  636. clocks = <&clk_usbphy1>, <&clk_usbehci1>, <&clk_usbhsic>, <&clk_usbhsic12m>, <&clk_pll_hsic>;
  637. hci_ctrl_no = <1>;
  638. status = "okay";
  639. };
  640.  
  641. ohci1:ohci1-controller@0x01c1b400 {
  642. compatible = "allwinner,sun50i-ohci1";
  643. reg = <0x0 0x01c1b000 0x0 0xFFF>, /*hci1 base*/
  644. <0x0 0x01c00000 0x0 0x100>, /*sram base*/
  645. <0x0 0x01c19000 0x0 0x1000>; /*otg base*/
  646. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  647. clocks = <&clk_usbphy1>, <&clk_usbohci1>;
  648. hci_ctrl_no = <1>;
  649. status = "okay";
  650. };
  651. codec:codec@0x01c22c00 {
  652. compatible = "allwinner,sunxi-internal-codec";
  653. reg = <0x0 0x01c22c00 0x0 0x478>,/*digital baseadress*/
  654. <0x0 0x01f015c0 0x0 0x0>;/*analog baseadress*/
  655. clocks = <&clk_pll_audiox4>;
  656.  
  657. pinctrl-names = "aif2-default","aif3-default","aif2-sleep","aif3-sleep";
  658. pinctrl-0 = <&aif2_pins_a>;
  659. pinctrl-1 = <&aif3_pins_a>;
  660. pinctrl-2 = <&aif2_pins_b>;
  661. pinctrl-3 = <&aif3_pins_b>;
  662.  
  663. /*gpio-spk=<&pio 6 7 0>;*/
  664. gpio-spk = <&pio PH 7 1 1 1 1>;
  665.  
  666. headphonevol = <0x3b>;
  667. spkervol = <0x1b>;
  668. earpiecevol = <0x1e>;
  669. maingain = <0x4>;
  670. headsetmicgain = <0x4>;
  671. adcagc_cfg = <0x0>;
  672. adcdrc_cfg = <0x0>;
  673. adchpf_cfg = <0x0>;
  674. dacdrc_cfg = <0x0>;
  675. dachpf_cfg = <0x0>;
  676. aif1_lrlk_div = <0x40>;
  677. aif2_lrlk_div = <0x40>;
  678. aif2config = <0x0>;
  679. aif3config = <0x0>;
  680. pa_sleep_time = <0x15e>;
  681. status = "okay";
  682. };
  683.  
  684. i2s:i2s0-controller@0x01c22c00 {
  685. compatible = "allwinner,sunxi-internal-i2s";
  686. reg = <0x0 0x01c22c00 0x0 0x478>;/*digital baseadress*/
  687. clocks = <&clk_pll_audio>,<&clk_adda>;
  688. status = "okay";
  689. };
  690.  
  691. daudio0:daudio@0x01c22000 {
  692. compatible = "allwinner,sunxi-daudio";
  693. reg = <0x0 0x01c22000 0x0 0x58>;
  694. clocks = <&clk_pll_audio>,<&clk_i2s0>;
  695. pinctrl-names = "default","sleep";
  696. pinctrl-0 = <&daudio0_pins_a>;
  697. pinctrl-1 = <&daudio0_pins_b>;
  698. pcm_lrck_period = <0x20>;
  699. pcm_lrckr_period = <0x01>;
  700. slot_width_select = <0x20>;
  701. pcm_lsb_first = <0x0>;
  702. tx_data_mode = <0x0>;
  703. rx_data_mode = <0x0>;
  704. daudio_master = <0x04>;
  705. audio_format = <0x01>;
  706. signal_inversion = <0x01>;
  707. frametype = <0x0>;
  708. tdm_config = <0x01>;
  709. tdm_num = <0x0>;
  710. status = "okay";
  711. };
  712. daudio1:daudio@0x01c22400 {
  713. compatible = "allwinner,sunxi-daudio";
  714. reg = <0x0 0x01c22400 0x0 0x58>;
  715. pinctrl-names = "default","sleep";
  716. pinctrl-0 = <&daudio1_pins_a>;
  717. pinctrl-1 = <&daudio1_pins_b>;
  718. clocks = <&clk_pll_audio>,<&clk_i2s1>;
  719. pcm_lrck_period = <0x20>;
  720. pcm_lrckr_period = <0x01>;
  721. slot_width_select = <0x20>;
  722. pcm_lsb_first = <0x0>;
  723. tx_data_mode = <0x0>;
  724. rx_data_mode = <0x0>;
  725. daudio_master = <0x04>;
  726. audio_format = <0x01>;
  727. signal_inversion = <0x01>;
  728. frametype = <0x0>;
  729. tdm_config = <0x01>;
  730. tdm_num = <0x1>;
  731. status = "okay";
  732. };
  733. daudio2:daudio@0x01c22800{
  734. compatible = "allwinner,sunxi-tdmhdmi";
  735. reg = <0x0 0x01c22800 0x0 0x58>;
  736. clocks = <&clk_pll_audio>,<&clk_i2s2>;
  737. status = "okay";
  738. };
  739. spdif:spdif-controller@0x01c21000{
  740. compatible = "allwinner,sunxi-spdif";
  741. reg = <0x0 0x01c21000 0x0 0x38>;
  742. clocks = <&clk_pll_audio>,<&clk_spdif>;
  743. pinctrl-names = "default","sleep";
  744. pinctrl-0 = <&spdif_pins_a>;
  745. pinctrl-1 = <&spdif_pins_b>;
  746. status = "okay";
  747. };
  748. sndcodec:sound@0 {
  749. compatible = "allwinner,sunxi-codec-machine";
  750. interrupts = <GIC_SPI 28 4>;
  751. sunxi,i2s-controller = <&i2s>;
  752. sunxi,audio-codec = <&codec>;
  753. aif2fmt = <3>;
  754. aif3fmt = <3>;
  755. aif2master = <1>;
  756. hp_detect_case = <0x00>;
  757. status = "okay";
  758. };
  759.  
  760. snddaudio0:sound@1{
  761. compatible = "allwinner,sunxi-daudio0-machine";
  762. sunxi,daudio0-controller = <&daudio0>;
  763. status = "okay";
  764. };
  765. snddaudio1:sound@2{
  766. compatible = "allwinner,sunxi-daudio1-machine";
  767. sunxi,daudio1-controller = <&daudio1>;
  768. status = "okay";
  769. };
  770. sndhdmi:sound@3{
  771. compatible = "allwinner,sunxi-hdmi-machine";
  772. sunxi,hdmi-controller = <&daudio2>;
  773. status = "okay";
  774. };
  775.  
  776. sndspdif:sound@4{
  777. compatible = "allwinner,sunxi-spdif-machine";
  778. sunxi,spdif-controller = <&spdif>;
  779. status = "okay";
  780. };
  781.  
  782. spi0: spi@01c68000 {
  783. #address-cells = <1>;
  784. #size-cells = <0>;
  785. compatible = "allwinner,sun50i-spi";
  786. device_type = "spi0";
  787. reg = <0x0 0x01c68000 0x0 0x1000>;
  788. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  789. clocks = <&clk_pll_periph0>, <&clk_spi0>;
  790. clock-frequency = <100000000>;
  791. pinctrl-names = "default", "sleep";
  792. pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
  793. pinctrl-1 = <&spi0_pins_c>;
  794. spi0_cs_number = <1>;
  795. spi0_cs_bitmap = <1>;
  796. status = "disabled";
  797. };
  798.  
  799. spi1: spi@01c69000 {
  800. #address-cells = <1>;
  801. #size-cells = <0>;
  802. compatible = "allwinner,sun50i-spi";
  803. device_type = "spi1";
  804. reg = <0x0 0x01c69000 0x0 0x1000>;
  805. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  806. clocks = <&clk_pll_periph0>, <&clk_spi1>;
  807. clock-frequency = <100000000>;
  808. pinctrl-names = "default", "sleep";
  809. pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
  810. pinctrl-1 = <&spi1_pins_c>;
  811. spi1_cs_number = <1>;
  812. spi1_cs_bitmap = <1>;
  813. status = "disabled";
  814. };
  815.  
  816. sdc2: sdmmc@01C11000 {
  817. compatible = "allwinner,sun50i-sdmmc2";
  818. device_type = "sdc2";
  819. reg = <0x0 0x01C11000 0x0 0x1000>;
  820. interrupts = <GIC_SPI 62 0x0104>; /* */
  821. clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc2_mod>,<&clk_sdmmc2_bus>,<&clk_sdmmc2_rst>;
  822. clock-names = "osc24m","pll_periph","mmc","ahb","rst";
  823. pinctrl-names = "default","sleep";
  824. pinctrl-0 = <&sdc2_pins_a>;
  825. pinctrl-1 = <&sdc2_pins_b>;
  826. bus-width = <8>;
  827. /*mmc-ddr-1_8v;*/
  828. /*mmc-hs200-1_8v;*/
  829. /*mmc-hs400-1_8v;*/
  830. /*non-removable;*/
  831. /*max-frequency = <200000000>;*/
  832. max-frequency = <50000000>;
  833.  
  834. /*-- speed mode --*/
  835. /*sm0: DS26_SDR12*/
  836. /*sm1: HSSDR52_SDR25*/
  837. /*sm2: HSDDR52_DDR50*/
  838. /*sm3: HS200_SDR104*/
  839. /*sm4: HS400*/
  840. /*-- frequency point --
  841. /*f0: CLK_400K*/
  842. /*f1: CLK_25M*/
  843. /*f2: CLK_50M*/
  844. /*f3: CLK_100M*/
  845. /*f4: CLK_150M*/
  846. /*f5: CLK_200M*/
  847.  
  848. sdc_tm4_sm0_freq0 = <0>;
  849. sdc_tm4_sm0_freq1 = <0>;
  850. sdc_tm4_sm1_freq0 = <0x00000000>;
  851. sdc_tm4_sm1_freq1 = <0>;
  852. sdc_tm4_sm2_freq0 = <0x00000000>;
  853. sdc_tm4_sm2_freq1 = <0>;
  854. sdc_tm4_sm3_freq0 = <0x05000000>;
  855. sdc_tm4_sm3_freq1 = <0x00000005>;
  856. sdc_tm4_sm4_freq0 = <0x00050000>;
  857. sdc_tm4_sm4_freq1 = <0x00000004>;
  858.  
  859. /*vmmc-supply = <&reg_3p3v>;*/
  860. /*vqmc-supply = <&reg_3p3v>;*/
  861. /*vdmc-supply = <&reg_3p3v>;*/
  862. /*vmmc = "vcc-card";*/
  863. /*vqmc = "";*/
  864. /*vdmc = "";*/
  865. /*sunxi-power-save-mode;*/
  866. /*status = "disabled";*/
  867. status = "okay";
  868.  
  869. };
  870.  
  871. sdc0: sdmmc@01c0f000 {
  872. compatible = "allwinner,sun50i-sdmmc0";
  873. device_type = "sdc0";
  874. reg = <0x0 0x01c0f000 0x0 0x1000>; /* only sdmmc0 */
  875. interrupts = <GIC_SPI 60 0x0104>; /* */
  876. clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>,<&clk_sdmmc0_rst>;
  877. clock-names = "osc24m","pll_periph","mmc","ahb","rst";
  878. pinctrl-names = "default","sleep";
  879. pinctrl-0 = <&sdc0_pins_a>;
  880. pinctrl-1 = <&sdc0_pins_b>;
  881. max-frequency = <50000000>;
  882. bus-width = <4>;
  883. broken-cd;
  884. /*cd-inverted*/
  885. cd-gpios = <&pio PF 6 0 1 2 0>;
  886. /* vmmc-supply = <&reg_3p3v>;*/
  887. /* vqmc-supply = <&reg_3p3v>;*/
  888. /* vdmc-supply = <&reg_3p3v>;*/
  889. /*vmmc = "vcc-card";*/
  890. /*vqmc = "";*/
  891. /*vdmc = "";*/
  892. /*sd-uhs-sdr50;*/
  893. /*sd-uhs-ddr50;*/
  894. /*cap-sdio-irq;*/
  895. /*keep-power-in-suspend;*/
  896. /*ignore-pm-notify;*/
  897. /*sunxi-power-save-mode;*/
  898. /*sunxi-dly-400k = <1 0 0 0>; */
  899. /*sunxi-dly-26M = <1 0 0 0>;*/
  900. /*sunxi-dly-52M = <1 0 0 0>;*/
  901. /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
  902. /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
  903. /*sunxi-dly-104M = <1 0 0 0>;*/
  904. /*sunxi-dly-208M = <1 0 0 0>;*/
  905. /*sunxi-dly-104M-ddr = <1 0 0 0>;*/
  906. /*sunxi-dly-208M-ddr = <1 0 0 0>;*/
  907.  
  908. status = "okay";
  909. /*status = "disabled";*/
  910. };
  911.  
  912.  
  913. sdc1: sdmmc@1C10000 {
  914. compatible = "allwinner,sun50i-sdmmc1";
  915. device_type = "sdc1";
  916. reg = <0x0 0x1C10000 0x0 0x1000>;
  917. interrupts = <GIC_SPI 61 0x0104>; /* */
  918. clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc1_mod>,<&clk_sdmmc1_bus>,<&clk_sdmmc1_rst>;
  919. clock-names = "osc24m","pll_periph","mmc","ahb","rst";
  920. pinctrl-names = "default","sleep";
  921. pinctrl-0 = <&sdc1_pins_a>;
  922. pinctrl-1 = <&sdc1_pins_b>;
  923. max-frequency = <50000000>;
  924. bus-width = <4>;
  925. /*broken-cd;*/
  926. /*cd-inverted*/
  927. /*cd-gpios = <&pio PG 6 6 1 2 0>;*/
  928. /* vmmc-supply = <&reg_3p3v>;*/
  929. /* vqmc-supply = <&reg_3p3v>;*/
  930. /* vdmc-supply = <&reg_3p3v>;*/
  931. /*vmmc = "vcc-card";*/
  932. /*vqmc = "";*/
  933. /*vdmc = "";*/
  934. /*sd-uhs-sdr50;*/
  935. /*sd-uhs-ddr50;*/
  936. /*sd-uhs-sdr104;*/
  937. /*cap-sdio-irq;*/
  938. /*keep-power-in-suspend;*/
  939. /*ignore-pm-notify;*/
  940. /*sunxi-power-save-mode;*/
  941. /*sunxi-dly-400k = <1 0 0 0 0>; */
  942. /*sunxi-dly-26M = <1 0 0 0 0>;*/
  943. /*sunxi-dly-52M = <1 0 0 0 0>;*/
  944. sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
  945. /*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
  946. sunxi-dly-104M = <1 0 0 0 1>;
  947. /*sunxi-dly-208M = <1 1 0 0 0>;*/
  948. sunxi-dly-208M = <1 0 0 0 1>;
  949. /*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
  950. /*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
  951.  
  952.  
  953. status = "okay";
  954. /*status = "disabled";*/
  955. };
  956.  
  957.  
  958. disp: disp@01000000 {
  959. compatible = "allwinner,sun50i-disp";
  960. reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/
  961. <0x0 0x01c0c000 0x0 0x17fc>,/*lcd*/
  962. <0x0 0x01ca0000 0x0 0x10fc>;/*dsi*/
  963. interrupts = <GIC_SPI 86 0x0104>, <GIC_SPI 87 0x0104>,
  964. <GIC_SPI 89 0x0104>;/* for dsi */
  965. clocks = <&clk_de>,<&clk_tcon0>,
  966. <&clk_lvds>,<&clk_mipidsi>,<&clk_tcon1>;
  967.  
  968. status = "okay";
  969. };
  970.  
  971. lcd0: lcd0@01c0c000 {
  972. compatible = "allwinner,sunxi-lcd0";
  973. pinctrl-names = "active","sleep";
  974.  
  975. status = "okay";
  976. };
  977.  
  978. hdmi: hdmi@01ee0000 {
  979. compatible = "allwinner,sunxi-hdmi";
  980. reg = <0x0 0x01ee0000 0x0 0x20000>;
  981. clocks = <&clk_hdmi>,<&clk_hdmi_slow>;
  982. };
  983.  
  984. soc_tr: tr@01000000 {
  985. compatible = "allwinner,sun50i-tr";
  986. reg = <0x0 0x01000000 0x0 0x000200bc>;
  987. interrupts = <GIC_SPI 96 0x0104>;
  988. clocks = <&clk_de>;
  989. status = "okay";
  990. };
  991.  
  992. pwm: pwm@01c21400 {
  993. compatible = "allwinner,sunxi-pwm0";
  994. reg = <0x0 0x01c21400 0x0 0x3c>;
  995. pwm-number = <1>;
  996. pinctrl-names = "active", "sleep";
  997. };
  998.  
  999. boot_disp: boot_disp {
  1000. compatible = "allwinner,boot_disp";
  1001. };
  1002.  
  1003. csi_cci0:cci@0x01cb3000 {
  1004. compatible = "allwinner,sunxi-csi_cci";
  1005. reg = <0x0 0x01cb3000 0x0 0x1000>; /*0x01cb3000--0x01cb4000*/
  1006. interrupts = <GIC_SPI 85 4>;/*SUNXI_IRQ_CSI0_CCI (SUNXI_GIC_START + 85) = 117*/
  1007. status = "okay";
  1008. };
  1009. csi_res0:csi_res@0x01cb0000 {
  1010. compatible = "allwinner,sunxi-csi";
  1011. reg = <0x0 0x01cb0000 0x0 0x1000>;/*0x01cb0000--0x01cb1000*/
  1012. status = "okay";
  1013. };
  1014. csi0:vfe@0 {
  1015. device_type= "csi0";
  1016. compatible = "allwinner,sunxi-vfe";
  1017. interrupts = <GIC_SPI 84 4>;/*SUNXI_IRQ_CSI0 (SUNXI_GIC_START + 84 ) = 116*/
  1018. clocks = <&clk_csi_s>, <&clk_csi_m>,<&clk_csi_misc>,
  1019. <&clk_pll_periph0>,<&clk_hosc>,<&clk_pll_periph1>;
  1020. pinctrl-names = "default","sleep";
  1021. pinctrl-0 = <&csi0_pins_a>;
  1022. pinctrl-1 = <&csi0_pins_b>;
  1023. csi0_sensor_list = <0>;
  1024. csi0_mck = <&pio PE 1 1 0 1 0>; /*PE1 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
  1025. status = "okay";
  1026. csi0_dev0:dev@0{
  1027. csi0_dev0_mname = "ov5640";
  1028. csi0_dev0_twi_addr = <0x78>;
  1029. csi0_dev0_pos = "rear";
  1030. csi0_dev0_isp_used = <1>;
  1031. csi0_dev0_fmt = <0>;
  1032. csi0_dev0_stby_mode = <0>;
  1033. csi0_dev0_vflip = <0>;
  1034. csi0_dev0_hflip = <0>;
  1035. csi0_dev0_iovdd = "iovdd-csi";
  1036. csi0_dev0_iovdd_vol = <2800000>;
  1037. csi0_dev0_avdd = "avdd-csi";
  1038. csi0_dev0_avdd_vol = <2800000>;
  1039. csi0_dev0_dvdd = "dvdd-csi-18";
  1040. csi0_dev0_dvdd_vol = <1500000>;
  1041. csi0_dev0_afvdd = "";
  1042. csi0_dev0_afvdd_vol = <>;
  1043. csi0_dev0_power_en = <>;
  1044. csi0_dev0_reset = <&pio PE 14 1 0 1 0>; /*PE14 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
  1045. csi0_dev0_pwdn = <&pio PE 15 1 0 1 0>; /*PE15 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
  1046. csi0_dev0_flash_used = <1>;
  1047. csi0_dev0_flash_type = <2>;
  1048. csi0_dev0_flash_en = <>;
  1049. csi0_dev0_flash_mode = <>;
  1050. csi0_dev0_flvdd = "vdd-csi-led";
  1051. csi0_dev0_flvdd_vol = <3300000>;
  1052. csi0_dev0_af_pwdn = <>;
  1053. csi0_dev0_act_used = <0>;
  1054. csi0_dev0_act_name = "ad5820_act";
  1055. csi0_dev0_act_slave = <0x18>;
  1056. status = "okay";
  1057. };
  1058. csi0_dev1:dev@1{
  1059. csi0_dev1_mname = "";
  1060. csi0_dev1_twi_addr = <0x78>;
  1061. csi0_dev1_pos = "rear";
  1062. csi0_dev1_isp_used = <1>;
  1063. csi0_dev1_fmt = <0>;
  1064. csi0_dev1_stby_mode = <0>;
  1065. csi0_dev1_vflip = <0>;
  1066. csi0_dev1_hflip = <0>;
  1067. csi0_dev1_iovdd = "iovdd-csi";
  1068. csi0_dev1_iovdd_vol = <2800000>;
  1069. csi0_dev1_avdd = "avdd-csi";
  1070. csi0_dev1_avdd_vol = <2800000>;
  1071. csi0_dev1_dvdd = "dvdd-csi-18";
  1072. csi0_dev1_dvdd_vol = <1500000>;
  1073. csi0_dev1_afvdd = "";
  1074. csi0_dev1_afvdd_vol = <>;
  1075. csi0_dev1_power_en = <>;
  1076. csi0_dev1_reset = <>;
  1077. csi0_dev1_pwdn = <>;
  1078. csi0_dev1_flash_used = <1>;
  1079. csi0_dev1_flash_type = <2>;
  1080. csi0_dev1_flash_en = <>;
  1081. csi0_dev1_flash_mode = <>;
  1082. csi0_dev1_flvdd = "vdd-csi-led";
  1083. csi0_dev1_flvdd_vol = <3300000>;
  1084. csi0_dev1_af_pwdn = <>;
  1085. csi0_dev1_act_used = <0>;
  1086. csi0_dev1_act_name = "ad5820_act";
  1087. csi0_dev1_act_slave = <0x18>;
  1088. status = "disabled";
  1089. };
  1090. };
  1091. Vdevice: vdevice@0{
  1092. compatible = "allwinner,sun50i-vdevice";
  1093. pinctrl-names = "default";
  1094. pinctrl-0 = <&vdevice_pins_a>;
  1095. test-gpios = <&r_pio PL 0 1 2 3 4>;
  1096. status = "okay";
  1097. };
  1098. cryptoengine: ce@1c15000 {
  1099. compatible = "allwinner,sunxi-ce";
  1100. reg = <0x0 0x01c15000 0x0 0x80>, /* non-secure space */
  1101. <0x0 0x01c15800 0x0 0x80>; /* secure space */
  1102. interrupts = <GIC_SPI 94 0xff01>, /* non-secure space */
  1103. <GIC_SPI 80 0xff01>; /* secure space */
  1104. clock-frequency = <300000000>, /* 300MHz */
  1105. <200000000>; /* 200MHz for RSA */
  1106. clocks = <&clk_ce>, <&clk_pll_periph0x2>;
  1107. };
  1108. di:deinterlace@0x01e00000{
  1109. #address-cells = <1>;
  1110. #size-cells = <0>;
  1111. compatible = "allwinner,sunxi-deinterlace";
  1112. reg = <0x0 0x01e00000 0x0 0x77c>;
  1113. interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  1114. clocks = <&clk_deinterlace> ,<&clk_pll_periph0>;
  1115. status = "okay";
  1116. };
  1117. smc:smartcard@0x01c2c400{
  1118. #address-cells = <1>;
  1119. #size-cells = <0>;
  1120. compatible = "allwinner,sunxi-scr";
  1121. reg = <0x0 0x01c2c400 0x0 0x100>;
  1122. interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  1123. clocks = <&clk_scr>, <&clk_apb2>;
  1124. clock-frequency = <24000000>;
  1125. pinctrl-names = "default";
  1126. pinctrl-0 = <&scr_pins_a>;
  1127. status = "okay";
  1128. };
  1129. nmi:nmi@0x01f00c00{
  1130. #address-cells = <1>;
  1131. #size-cells = <0>;
  1132. compatible = "allwinner,sunxi-nmi";
  1133. reg = <0x0 0x01f00c00 0x0 0x50>;
  1134. nmi_irq_ctrl = <0x0c>;
  1135. nmi_irq_en = <0x40>;
  1136. nmi_irq_status = <0x10>;
  1137. nmi_irq_mask = <0x50>;
  1138. status = "okay";
  1139. };
  1140. pmu0:pmu0@0{
  1141. compatible = "allwinner,pmu0";
  1142. device_type = "pmu0";
  1143. pmu_batdeten = <1>;
  1144. pmu_init_chgend_rate = <20>;
  1145. pmu_init_chg_enabled = <1>;
  1146. pmu_init_adc_freq = <800>;
  1147. pmu_init_adcts_freq = <800>;
  1148. pmu_init_chg_pretime = <70>;
  1149. pmu_init_chg_csttime = <720>;
  1150. pmu_batt_cap_correct = <1>;
  1151. pmu_chg_end_on_en = <0>;
  1152.  
  1153. pmu_pwroff_vol = <3300>;
  1154. pmu_pwron_vol = <2600>;
  1155. pmu_powkey_off_delay_time = <0>;
  1156. pmu_pwrok_time = <64>;
  1157. pmu_reset_shutdown_en = <1>;
  1158. pmu_restvol_adjust_time = <60>;
  1159. pmu_ocv_cou_adjust_time = <60>;
  1160. pmu_vbusen_func = <1>;
  1161. pmu_reset = <0>;
  1162. pmu_IRQ_wakeup = <0>;
  1163. pmu_hot_shutdowm = <1>;
  1164. pmu_inshort = <0>;
  1165. pmu_bat_shutdown_ltf = <3200>; /* add by superm for debug */
  1166. pmu_bat_shutdown_htf = <237>; /* add by superm for debug */
  1167. status = "okay";
  1168. };
  1169. pmu0_regu:regu@0{
  1170. compatible = "allwinner,pmu0_regu";
  1171. regulator_count = <23>;
  1172. status = "okay";
  1173. };
  1174.  
  1175. nand0:nand0@01c03000 {
  1176. compatible = "allwinner,sun50i-nand";
  1177. device_type = "nand0";
  1178. reg = <0x0 0x01c03000 0x0 0x1000>; /* nand0 */
  1179. interrupts = <GIC_SPI 70 0x04>;
  1180. clocks = <&clk_pll_periph0>,<&clk_nand>;
  1181. pinctrl-names = "default", "sleep";
  1182. pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
  1183. pinctrl-1 = <&nand0_pins_c>;
  1184. nand0_regulator1 = "vcc-nand";
  1185. nand0_regulator2 = "none";
  1186. nand0_cache_level = <0x55aaaa55>;
  1187. nand0_flush_cache_num = <0x55aaaa55>;
  1188. nand0_capacity_level = <0x55aaaa55>;
  1189. nand0_id_number_ctl = <0x55aaaa55>;
  1190. nand0_print_level = <0x55aaaa55>;
  1191. nand0_p0 = <0x55aaaa55>;
  1192. nand0_p1 = <0x55aaaa55>;
  1193. nand0_p2 = <0x55aaaa55>;
  1194. nand0_p3 = <0x55aaaa55>;
  1195. status = "okay";
  1196. };
  1197.  
  1198. sunxi_thermal_sensor:thermal_sensor{
  1199. compatible = "allwinner,thermal_sensor";
  1200. reg = <0x0 0x01c25000 0x0 0x400>;
  1201. interrupts = <GIC_SPI 31 IRQ_TYPE_NONE>;
  1202. clocks = <&clk_hosc>,<&clk_ths>;
  1203. sensor_num = <3>;
  1204. shut_temp= <120>;
  1205. status = "okay";
  1206.  
  1207. combine0:combine0{
  1208. #thermal-sensor-cells = <1>;
  1209. combine_cnt = <3>;
  1210. combine_type = "max";
  1211. combine_chn = <0 1 2>;
  1212. };
  1213. };
  1214.  
  1215. cpu_budget_cooling:cpu_budget_cool{
  1216. compatible = "allwinner,budget_cooling";
  1217. #cooling-cells = <2>;
  1218. status = "okay";
  1219. state_cnt = <7>;
  1220. cluster_num = <1>;
  1221. state0 = <1152000 4>;
  1222. state1 = <1104000 4>;
  1223. state2 = <1008000 4>;
  1224. state3 = <816000 4>;
  1225. state4 = <648000 4>;
  1226. state5 = <648000 2>;
  1227. state6 = <648000 1>;
  1228. };
  1229.  
  1230. gpu_cooling:gpu_cooling{
  1231. compatible = "allwinner,gpu_cooling";
  1232. reg = <0x0 0x0 0x0 0x0>;
  1233. #cooling-cells = <2>;
  1234. status = "okay";
  1235. state_cnt = <3>;
  1236. state0 = <0>;
  1237. state1 = <360>;
  1238. state2 = <144>;
  1239. };
  1240.  
  1241. thermal-zones{
  1242. soc_thermal{
  1243.  
  1244. polling-delay-passive = <500>;
  1245. polling-delay = <2000>;
  1246. thermal-sensors = <&combine0 0>;
  1247.  
  1248. trips{
  1249. cpu_trip0:t0{
  1250. temperature = <65>;
  1251. type = "passive";
  1252. hysteresis = <0>;
  1253. };
  1254. cpu_trip1:t1{
  1255. temperature = <80>;
  1256. type = "passive";
  1257. hysteresis = <0>;
  1258. };
  1259. cpu_trip2:t2{
  1260. temperature = <90>;
  1261. type = "passive";
  1262. hysteresis = <0>;
  1263. };
  1264. cpu_trip3:t3{
  1265. temperature = <100>;
  1266. type = "passive";
  1267. hysteresis = <0>;
  1268. };
  1269. gpu_trip0:t4{
  1270. temperature = <85>;
  1271. type = "passive";
  1272. hysteresis = <0>;
  1273. };
  1274. gpu_trip1:t5{
  1275. temperature = <95>;
  1276. type = "passive";
  1277. hysteresis = <0>;
  1278. };
  1279. crt_trip:t6{
  1280. temperature = <110>;
  1281. type = "critical";
  1282. hysteresis = <0>;
  1283. };
  1284. };
  1285.  
  1286. cooling-maps{
  1287. bind0{
  1288. contribution = <0>;
  1289. trip = <&cpu_trip0>;
  1290. cooling-device = <&cpu_budget_cooling 1 1>;
  1291. };
  1292. bind1{
  1293. contribution = <0>;
  1294. trip = <&cpu_trip1>;
  1295. cooling-device = <&cpu_budget_cooling 2 2>;
  1296. };
  1297. bind2{
  1298. contribution = <0>;
  1299. trip = <&cpu_trip2>;
  1300. cooling-device = <&cpu_budget_cooling 3 4>;
  1301. };
  1302. bind3{
  1303. contribution = <0>;
  1304. trip = <&cpu_trip3>;
  1305. cooling-device = <&cpu_budget_cooling 5 6>;
  1306. };
  1307. bind4{
  1308. contribution = <0>;
  1309. trip = <&gpu_trip0>;
  1310. cooling-device = <&gpu_cooling 1 1>;
  1311. };
  1312. bind5{
  1313. contribution = <0>;
  1314. trip = <&gpu_trip1>;
  1315. cooling-device = <&gpu_cooling 2 2>;
  1316. };
  1317. };
  1318. };
  1319. };
  1320.  
  1321. keyboard0:keyboard{
  1322. compatible = "allwinner,keyboard_2000mv";
  1323. reg = <0x0 0x01c21800 0x0 0x400>;
  1324. interrupts = <GIC_SPI 30 IRQ_TYPE_NONE>;
  1325. status = "okay";
  1326. key_cnt = <5>;
  1327. key1 = <240 115>;
  1328. key2 = <500 114>;
  1329. key3 = <700 139>;
  1330. key4 = <890 28>;
  1331. key5 = <2000 102>;
  1332. };
  1333.  
  1334. gmac0: eth@01c30000 {
  1335. compatible = "allwinner,sunxi-gmac";
  1336. reg = <0x0 0x01c30000 0x0 0x40000>,
  1337. <0x0 0x01c00000 0x0 0x30>;
  1338. pinctrl-names = "default";
  1339. pinctrl-0 = <&gmac_pins_a>;
  1340. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  1341. interrupt-names = "gmacirq";
  1342. clocks = <&clk_gmac>;
  1343. clock-names = "gmac";
  1344. phy-mode = "rgmii";
  1345. tx-delay = <7>;
  1346. rx-delay = <31>;
  1347. gmac_power1 = "axp81x_dldo2:2500000";
  1348. gmac_power2 = "axp81x_eldo2:1800000";
  1349. gmac_power3 = "axp81x_fldo1:1200000";
  1350. status = "disable";
  1351. };
  1352. };
  1353. };
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