library ieee;
use ieee.std_logic_1164.all;
entity c is

  port (
    o : out std_ulogic;
    c : in  std_ulogic;
    i : in  std_ulogic);

end entity c;

architecture rtl of c is

begin  -- architecture rtl

  process (c) is
  begin
    if rising_edge(c) then
      o <= i xor o;
    end if;
  end process;

end architecture rtl;