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TI814x: SATA: Provide 100MHz input clock to SATA instead of

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  1. From: Sriramakrishnan A G <[email protected]>
  2. Date: Mon, 7 May 2012 12:13:27 +0000 (+0530)
  3. Subject: TI814x: SATA: Provide 100MHz input clock to SATA instead of 20Mhz
  4. X-Git-Url: http://arago-project.org/git/projects/?p=linux-omap3.git;a=commitdiff_plain;h=ee3f09c0604b947e5307d810df3a10f8047729e8
  5.  
  6. TI814x: SATA: Provide 100MHz input clock to SATA instead of 20Mhz
  7.  
  8. By default, 20MHz internal clock is provided to SATA PHY.
  9. We observed some jitter issues with this internal clock.
  10. Hence we are providing 100MHz clock from PCIe output as input
  11. to SATA. This solved the jitter issues and basic SATA
  12. read/write interface fatal error issues.
  13.  
  14. Signed-off-by: Basheer, Mansoor Ahamed <[email protected]>
  15. Signed-off-by: Sriramakrishnan A G <[email protected]>
  16. ---
  17.  
  18. diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
  19. index a0612c4..89e6f7b 100644
  20. --- a/arch/arm/mach-omap2/control.h
  21. +++ b/arch/arm/mach-omap2/control.h
  22. @@ -277,6 +277,20 @@
  23.  #define TI814X_CONTROL_PCIE_CFG        0x0480
  24.  #define TI814X_CONTROL_SMA0        0x1318
  25.  
  26. +
  27. +#define TI814X_CONTROL_SATA_PLLCFG0    (TI81XX_CONTROL_DEVCONF + 0x120)
  28. +#define TI814X_CONTROL_SATA_PLLCFG1    (TI81XX_CONTROL_DEVCONF + 0x124)
  29. +#define TI814X_CONTROL_SATA_PLLCFG2    (TI81XX_CONTROL_DEVCONF + 0x128)
  30. +#define TI814X_CONTROL_SATA_PLLCFG3    (TI81XX_CONTROL_DEVCONF + 0x12c)
  31. +#define TI814X_CONTROL_SATA_PLLCFG4    (TI81XX_CONTROL_DEVCONF + 0x130)
  32. +#define TI814X_CONTROL_SATA_PLLSTATUS  (TI81XX_CONTROL_DEVCONF + 0x134)
  33. +#define TI814X_CONTROL_SATA_RXSTATUS   (TI81XX_CONTROL_DEVCONF + 0x138)
  34. +#define TI814X_CONTROL_SATA_TXSTATUS   (TI81XX_CONTROL_DEVCONF + 0x13c)
  35. +#define TI814X_CONTROL_SATA_TESTCFG    (TI81XX_CONTROL_DEVCONF + 0x140)
  36. +
  37. +
  38. +
  39. +
  40.  /* TI816X PLL Control register offsets */
  41.  #define TI816X_MAINPLL_CTRL        TI81XX_CTRL_REGADDR(0x0400)
  42.  #define TI816X_MAINPLL_PWD     TI81XX_CTRL_REGADDR(0x0404)
  43. diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
  44. index 7fe5488..3610a60 100644
  45. --- a/arch/arm/mach-omap2/devices.c
  46. +++ b/arch/arm/mach-omap2/devices.c
  47. @@ -25,6 +25,7 @@
  48.  #include <asm/mach-types.h>
  49.  #include <asm/mach/map.h>
  50.  #include <asm/pmu.h>
  51. +#include <asm/delay.h>
  52.  #include <asm/hardware/edma.h>
  53.  
  54.  #include <plat/tc.h>
  55. @@ -2255,6 +2256,76 @@ static void ti81xx_ethernet_init(void)
  56.     else
  57.         ti814x_cpsw_init();
  58.  }
  59. +
  60. +static inline void ti814x_sata_pllcfg(void)
  61. +{
  62. +   if (cpu_is_ti814x()) {
  63. +       /* Configure SATA0 PLL -applies for TI814x*/
  64. +       omap_ctrl_writel(0x00000004, TI814X_CONTROL_SATA_PLLCFG0);
  65. +       udelay(100);
  66. +       /* cfgpll1  (for 100 MHz Operation) */
  67. +       omap_ctrl_writel(0x812C003C, TI814X_CONTROL_SATA_PLLCFG1);
  68. +       udelay(2000);
  69. +       omap_ctrl_writel(0x004008E0, TI814X_CONTROL_SATA_PLLCFG3);
  70. +       udelay(2000);
  71. +       /* wait for bias to be stable */
  72. +       omap_ctrl_writel(0x00000014, TI814X_CONTROL_SATA_PLLCFG0);
  73. +       udelay(850);
  74. +       omap_ctrl_writel(0x00000016, TI814X_CONTROL_SATA_PLLCFG0);
  75. +       udelay(60);
  76. +       /* cfgpll0 Replaced 0xC00000016 to 0x40000016 for 100MHz
  77. +       * Usage instead of 20MHz
  78. +       */
  79. +       omap_ctrl_writel(0x40000016, TI814X_CONTROL_SATA_PLLCFG0);
  80. +       udelay(2000);
  81. +
  82. +       /* cfgpll0 Replaced 0xC0007077 with 0x40007077 for
  83. +       * 100MHz Usage instead of 20MHz
  84. +       */
  85. +       omap_ctrl_writel(0x40007077, TI814X_CONTROL_SATA_PLLCFG0);
  86. +
  87. +       while (!(omap_ctrl_readl(TI814X_CONTROL_SATA_PLLSTATUS) & 0x1))
  88. +           cpu_relax();
  89. +   }
  90. +
  91. +}
  92. +
  93. +static inline void ti814x_pcie_pllcfg(void)
  94. +{
  95. +   if (cpu_is_ti814x()) {
  96. +       /* TODO: Add bitfield macros for following */
  97. +       omap_ctrl_writel(0x00000002, TI814X_SERDES_REFCLK_CTL);
  98. +       omap_ctrl_writel(0x00000000, TI814X_CONTROL_PCIE_PLLCFG0);
  99. +       omap_ctrl_writel(0x0064003C, TI814X_CONTROL_PCIE_PLLCFG1);
  100. +       omap_ctrl_writel(0x00000000, TI814X_CONTROL_PCIE_PLLCFG2);
  101. +       omap_ctrl_writel(0x004008E0, TI814X_CONTROL_PCIE_PLLCFG3);
  102. +       omap_ctrl_writel(0x0000609C, TI814X_CONTROL_PCIE_PLLCFG4);
  103. +
  104. +       /* Configure SERDES misc bits - values as is from h/w */
  105. +       if (omap_rev() > TI8148_REV_ES1_0) {
  106. +           omap_ctrl_writel(0x0000039E,
  107. +               TI814X_CONTROL_PCIE_MISCCFG);
  108. +       } else
  109. +           omap_ctrl_writel(0x00000E7B, TI814X_CONTROL_SMA0);
  110. +
  111. +       udelay(50);
  112. +       omap_ctrl_writel(0x00000004, TI814X_CONTROL_PCIE_PLLCFG0);
  113. +       udelay(50);
  114. +       omap_ctrl_writel(0x00000014, TI814X_CONTROL_PCIE_PLLCFG0);
  115. +       udelay(50);
  116. +       omap_ctrl_writel(0x00000016, TI814X_CONTROL_PCIE_PLLCFG0);
  117. +       udelay(50);
  118. +       omap_ctrl_writel(0x30000016, TI814X_CONTROL_PCIE_PLLCFG0);
  119. +       udelay(50);
  120. +       omap_ctrl_writel(0x70007016, TI814X_CONTROL_PCIE_PLLCFG0);
  121. +       udelay(50);
  122. +       omap_ctrl_writel(0x70007017, TI814X_CONTROL_PCIE_PLLCFG0);
  123. +       udelay(200);
  124. +       /* poll the status field to check if pll lock occured. */
  125. +       while (!(omap_ctrl_readl(TI814X_CONTROL_PCIE_PLLSTATUS) & 0x1))
  126. +           cpu_relax();
  127. +   }
  128. +}
  129.  #endif
  130.  
  131.  #if defined(CONFIG_SATA_AHCI_PLATFORM) || \
  132. @@ -2288,13 +2359,16 @@ static struct clk *omap_sata_clk;
  133.  /* These values are tried and tested and not expected to change.
  134.   * Hence not using a macro to generate them.
  135.   */
  136. -#define TI814X_SATA_PHY_CFGRX0_VAL     0x00C7CC22
  137. -#define TI814X_SATA_PHY_CFGRX1_VAL     0x008E0500
  138. -#define TI814X_SATA_PHY_CFGRX2_VAL     0x7BDEF000
  139. -#define TI814X_SATA_PHY_CFGRX3_VAL     0x1F180B0F
  140. -#define TI814X_SATA_PHY_CFGTX0_VAL     0x01001622
  141. -#define TI814X_SATA_PHY_CFGTX1_VAL     0x40000002
  142. -#define TI814X_SATA_PHY_CFGTX2_VAL     0x073CE39E
  143. +#define TI814X_SATA_PHY_CFGRX0_VAL      0x008FCC22
  144. +#define TI814X_SATA_PHY_CFGRX1_VAL      0x008E0500
  145. +#define TI814X_SATA_PHY_CFGRX2_VAL      0x7BDEF000
  146. +#define TI814X_SATA_PHY_CFGRX3_VAL      0x1F180B0F
  147. +#define TI814X_SATA_PHY_CFGTX0_VAL      0x01003622
  148. +#define TI814X_SATA_PHY_CFGTX1_VAL      0x40000002
  149. +#define TI814X_SATA_PHY_CFGTX2_VAL      0x00C201F8
  150. +#define TI814X_SATA_PHY_CFGTX3_VAL      0x073CE39E
  151. +
  152. +
  153.  
  154.  static int ti81xx_ahci_plat_init(struct device *dev, void __iomem *base)
  155.  {
  156. @@ -2313,10 +2387,12 @@ static int ti81xx_ahci_plat_init(struct device *dev, void __iomem *base)
  157.         goto err;
  158.     }
  159.  
  160. -   ret = clk_enable(omap_sata_clk);
  161. -   if (ret) {
  162. -       pr_err("ahci : Clock enable failed\n");
  163. -       goto err;
  164. +   if (!cpu_is_ti814x()) {
  165. +       ret = clk_enable(omap_sata_clk);
  166. +       if (ret) {
  167. +           pr_err("ahci : Clock enable failed\n");
  168. +           goto err;
  169. +       }
  170.     }
  171.  
  172.     if (cpu_is_ti816x()) {
  173. @@ -2338,7 +2414,23 @@ static int ti81xx_ahci_plat_init(struct device *dev, void __iomem *base)
  174.         writel(phy_val, base + SATA_P0PHYCR_REG);
  175.         writel(phy_val, base + SATA_P1PHYCR_REG);
  176.     } else if (cpu_is_ti814x()) {
  177. -       /* Configuring TI814X SATA PHY */
  178. +
  179. +
  180. +       ret = clk_enable(omap_sata_clk);
  181. +       if (ret) {
  182. +           pr_err("ahci : Clock enable failed\n");
  183. +           goto err;
  184. +       }
  185. +
  186. +       /* configure the SATA PHY */
  187. +       writel(TI814X_SATA_PHY_CFGTX0_VAL,
  188. +           base + TI814X_SATA_PHY_CFGTX0_OFFSET);
  189. +       writel(TI814X_SATA_PHY_CFGTX1_VAL,
  190. +           base + TI814X_SATA_PHY_CFGTX1_OFFSET);
  191. +       writel(TI814X_SATA_PHY_CFGTX2_VAL,
  192. +           base + TI814X_SATA_PHY_CFGTX2_OFFSET);
  193. +       writel(TI814X_SATA_PHY_CFGTX3_VAL,
  194. +           base + TI814X_SATA_PHY_CFGTX3_OFFSET);
  195.         writel(TI814X_SATA_PHY_CFGRX0_VAL,
  196.             base + TI814X_SATA_PHY_CFGRX0_OFFSET);
  197.         writel(TI814X_SATA_PHY_CFGRX1_VAL,
  198. @@ -2347,12 +2439,6 @@ static int ti81xx_ahci_plat_init(struct device *dev, void __iomem *base)
  199.             base + TI814X_SATA_PHY_CFGRX2_OFFSET);
  200.         writel(TI814X_SATA_PHY_CFGRX3_VAL,
  201.             base + TI814X_SATA_PHY_CFGRX3_OFFSET);
  202. -       writel(TI814X_SATA_PHY_CFGTX0_VAL,
  203. -           base + TI814X_SATA_PHY_CFGTX0_OFFSET);
  204. -       writel(TI814X_SATA_PHY_CFGTX1_VAL,
  205. -           base + TI814X_SATA_PHY_CFGTX1_OFFSET);
  206. -       writel(TI814X_SATA_PHY_CFGTX2_VAL,
  207. -           base + TI814X_SATA_PHY_CFGTX2_OFFSET);
  208.     }
  209.  
  210.     return 0;
  211. @@ -2524,42 +2610,7 @@ static inline void ti81xx_init_pcie(void)
  212.     } else if (cpu_is_ti814x()) {
  213.  
  214.         /* TODO: Add bitfield macros for following */
  215. -
  216. -       omap_ctrl_writel(0x00000002, TI814X_SERDES_REFCLK_CTL);
  217. -       omap_ctrl_writel(0x00000000, TI814X_CONTROL_PCIE_PLLCFG0);
  218. -       omap_ctrl_writel(0x00640000, TI814X_CONTROL_PCIE_PLLCFG1);
  219. -       omap_ctrl_writel(0x00000000, TI814X_CONTROL_PCIE_PLLCFG2);
  220. -       omap_ctrl_writel(0x004008E0, TI814X_CONTROL_PCIE_PLLCFG3);
  221. -       omap_ctrl_writel(0x0000609C, TI814X_CONTROL_PCIE_PLLCFG4);
  222. -
  223. -       /* Configure SERDES misc bits - values as is from h/w */
  224. -       if (omap_rev() > TI8148_REV_ES1_0)
  225. -           omap_ctrl_writel(0x0000039E,
  226. -                   TI814X_CONTROL_PCIE_MISCCFG);
  227. -       else
  228. -           omap_ctrl_writel(0x00000E7B, TI814X_CONTROL_SMA0);
  229. -
  230. -       udelay(50);
  231. -       omap_ctrl_writel(0x00000004, TI814X_CONTROL_PCIE_PLLCFG0);
  232. -
  233. -       udelay(50);
  234. -       omap_ctrl_writel(0x00000014, TI814X_CONTROL_PCIE_PLLCFG0);
  235. -
  236. -       udelay(50);
  237. -       omap_ctrl_writel(0x00000016, TI814X_CONTROL_PCIE_PLLCFG0);
  238. -
  239. -       udelay(50);
  240. -       omap_ctrl_writel(0x30000016, TI814X_CONTROL_PCIE_PLLCFG0);
  241. -
  242. -       udelay(50);
  243. -       omap_ctrl_writel(0x70007016, TI814X_CONTROL_PCIE_PLLCFG0);
  244. -
  245. -       udelay(200);
  246. -       omap_ctrl_writel(0x70007017, TI814X_CONTROL_PCIE_PLLCFG0);
  247. -
  248. -       while (!(omap_ctrl_readl(TI814X_CONTROL_PCIE_PLLSTATUS) & 0x1))
  249. -           cpu_relax();
  250. -
  251. +       /* PLL configuration has be done by now */
  252.         omap_ctrl_writel(TI81XX_PCIE_DEVTYPE_RC,
  253.                 TI814X_CONTROL_PCIE_CFG);
  254.  
  255. @@ -2692,6 +2743,11 @@ static int __init omap2_init_devices(void)
  256.     omap_init_aes();
  257.     omap_init_vout();
  258.  #ifdef CONFIG_ARCH_TI81XX
  259. +   if (cpu_is_ti814x()) {
  260. +       /* Init PCIe,SATA PLL here, before invoking respective init*/
  261. +       ti814x_pcie_pllcfg();
  262. +       ti814x_sata_pllcfg();
  263. +   }
  264.     ti81xx_ethernet_init();
  265.     ti81xx_init_pcie();
  266.     ti81xx_register_edma();
  267. diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/plat-omap/include/plat/ti81xx.h
  268. index c1b333a..1907b16 100644
  269. --- a/arch/arm/plat-omap/include/plat/ti81xx.h
  270. +++ b/arch/arm/plat-omap/include/plat/ti81xx.h
  271. @@ -60,7 +60,8 @@
  272.  #define TI814X_SATA_PHY_CFGRX3_OFFSET  (0x1110)
  273.  #define TI814X_SATA_PHY_CFGTX0_OFFSET  (0x111C)
  274.  #define TI814X_SATA_PHY_CFGTX1_OFFSET  (0x1120)
  275. -#define TI814X_SATA_PHY_CFGTX2_OFFSET  (0x1128)
  276. +#define TI814X_SATA_PHY_CFGTX2_OFFSET  (0x1124)
  277. +#define TI814X_SATA_PHY_CFGTX3_OFFSET  (0x1128)
  278.  
  279.  #define TI81XX_MC_MMU_BASE 0x55082000
  280.  #define TI81XX_SYS_MMU_BASE    0x48010000
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