module top {
    input iCLK,
    input iSW,
    output reg [7:0] oLED
};

reg [28:0] rCnt;
reg rLR; // 0 left 1 right
reg [3:0] rRega;

always @( posedge rCnt[23] ) begin
    if (iSW==1) begin
        case (rRega)
            0: oLED = 8'h0;
            1: oLED = 8'h18;
            2: oLED = 8'h24;
            3: oLED = 8'h42;
            4: oLED = 8'h81;
            default oLED = 0;
        endcase
    else begin
        case (rRega)
            0: oLED = 8'h81 ;
            1: oLED = 8'h42 ;
            2: oLED = 8'h24;
            3: oLED = 8'h18;
            4: oLED = 8'h0;
            default oLED = 0;
        endcase
    end
    rRega = rRega + 1;
    if ( rRega == 4 ) rRega = 0;
end

always @( posedge iCLK ) rCnt = rCnt + 1;
endmodule