Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- /*
- * Copyright (c) 2010, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
- /*
- * ======== all.cfg ========
- *
- * For details about the packages and configuration parameters used throughout
- * this config script, see the Codec Engine Configuration Guide (link
- * provided in the release notes).
- */
- /*
- * Configure CE's OSAL. This codec server only builds for the BIOS-side of
- * a heterogeneous system, so use the "DSPLINK_BIOS" configuration.
- */
- var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
- osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;
- /* configure default memory seg id to BIOS-defined segment */
- var platform = Program.build.cfgArgs.platform;
- if (platform.match("evmOMAPL13[78]")) {
- osalGlobal.defaultMemSegId = "SDRAM";
- }
- else {
- osalGlobal.defaultMemSegId = "DDR2";
- }
- /*
- * Uncomment and modify the following line, to change the size of the circular
- * trace buffer, if necessary.
- */
- //osalGlobal.traceBufferSize = 32 * 1024;
- /* activate BIOS logging module */
- var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer');
- /* configure power management */
- var cfgArgs = Program.build.cfgArgs;
- if ((cfgArgs != undefined) && (cfgArgs.usePowerManagement != undefined)) {
- var biosIpc = xdc.useModule('ti.sdo.ce.ipc.bios.Ipc');
- biosIpc.usePowerManagement = cfgArgs.usePowerManagement;
- }
- /*
- * "Use" the various codec modules; i.e., implementation of codecs.
- * All these "xdc.useModule" commands provide a handle to the codecs,
- * which we'll use below to add them to the Server.algs array.
- */
- var H264DEC =
- xdc.useModule('ti.sdo.codecs.h264dec.ce.H264DEC');
- var VIDDEC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.viddec_copy.VIDDEC_COPY');
- var VIDENC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.videnc_copy.VIDENC_COPY');
- var SPHENC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.sphenc_copy.SPHENC_COPY');
- var SPHDEC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.sphdec_copy.SPHDEC_COPY');
- var IMGDEC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.imgdec_copy.IMGDEC_COPY');
- var IMGENC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.imgenc_copy.IMGENC_COPY');
- var AUDDEC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.auddec_copy.AUDDEC_COPY');
- var AUDENC_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.audenc_copy.AUDENC_COPY');
- var SCALE = xdc.useModule('ti.sdo.ce.examples.codecs.scale.SCALE_TI');
- var VIDDEC2_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.viddec2_copy.VIDDEC2_COPY');
- var VIDENC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.videnc1_copy.VIDENC1_COPY');
- var IMGDEC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.imgdec1_copy.IMGDEC1_COPY');
- var IMGENC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.imgenc1_copy.IMGENC1_COPY');
- var SPHENC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.sphenc1_copy.SPHENC1_COPY');
- var SPHDEC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.sphdec1_copy.SPHDEC1_COPY');
- var AUDDEC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.auddec1_copy.AUDDEC1_COPY');
- var AUDENC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.audenc1_copy.AUDENC1_COPY');
- var G711ENC = xdc.useModule('ti.sdo.ce.examples.codecs.g711.G711ENC');
- var G711DEC = xdc.useModule('ti.sdo.ce.examples.codecs.g711.G711DEC');
- var transcoder = xdc.useModule('ti.sdo.ce.examples.codecs.' +
- 'vidtranscode_copy.VIDTRANSCODE_COPY');
- var analytics = xdc.useModule('ti.sdo.ce.examples.codecs.' +
- 'vidanalytics_copy.VIDANALYTICS_COPY');
- var universal = xdc.useModule('ti.sdo.ce.examples.codecs.' +
- 'universal_copy.UNIVERSAL_COPY');
- var VIDDEC1_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.viddec1_copy.VIDDEC1_COPY');
- var VIDDEC2BACK_COPY =
- xdc.useModule('ti.sdo.ce.examples.codecs.viddec2split_copy.VIDDEC2BACK_COPY');
- /*
- * ======== Server Configuration ========
- */
- var Server = xdc.useModule('ti.sdo.ce.Server');
- /*
- * Set the caching policy that will be used by all skeletons. The options
- * are the following:
- *
- * LOCALBUFFERINVWB - Cache invalidation will be performed on input and
- * output buffers before processing, a cache writeback
- * will be performed on output buffers after processing.
- * This is the default policy, if this configuration
- * parameter is not set in the cfg file.
- *
- * WBINVALL - Perform a cache writeback invalidate on all memory
- * after processing. No invalidation of buffers is
- * done before processing. This may be more efficient
- * than the LOCALBUFFERINVWB policy in cases of very
- * large buffers.
- *
- * NONE - No cache operations will be performed in the
- * skeletons.
- */
- Server.skelCachingPolicy = Server.LOCALBUFFERINVWB;
- //Server.skelCachingPolicy = Server.WBINVALL;
- /* The server's stackSize. More than we need... but safe. */
- Server.threadAttrs.stackSize = 4096;
- /* The servers execution priority */
- Server.threadAttrs.priority = Server.MINPRI;
- /*
- * The optional stack pad to add to non-configured stacks. This is well
- * beyond most codec needs, but follows the approach of "start big and
- * safe, then optimize when things are working."
- */
- Server.stackSizePad = 9000;
- /*
- * The array of algorithms this server can serve up. This array also
- * configures details about the threads which will be created to run the
- * algorithms (e.g. stack sizes, priorities, etc.).
- *
- * Note that we don't set any per-codec instance stack sizes below, as
- * we leverage the Server.stackSizePad config param to pad all stacks in
- * this simple example.
- *
- * However, in a 'real' server, stack sizes should be measured and
- * tested - there are some techniques for doing so here:
- * http://wiki.davincidsp.com/index.php?title=Stack_issues
- */
- Server.algs = [
- {name: "viddec_copy", mod: VIDDEC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "videnc_copy", mod: VIDENC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "imgdec_copy", mod: IMGDEC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 2}, groupId : 1,
- },
- {name: "imgenc_copy", mod: IMGENC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 2}, groupId : 1,
- },
- {name: "auddec_copy", mod: AUDDEC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "audenc_copy", mod: AUDENC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "sphenc_copy", mod: SPHENC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "sphdec_copy", mod: SPHDEC_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "scale", mod: SCALE, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}
- },
- {name: "h264dec", mod: H264DEC, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "viddec2_copy", mod: VIDDEC2_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "videnc1_copy", mod: VIDENC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "imgdec1_copy", mod: IMGDEC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 2}, groupId : 1,
- },
- {name: "imgenc1_copy", mod: IMGENC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 2}, groupId : 1,
- },
- {name: "sphdec1_copy", mod: SPHDEC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "sphenc1_copy", mod: SPHENC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "auddec1_copy", mod: AUDDEC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "audenc1_copy", mod: AUDENC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "g711enc", mod: G711ENC, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "g711dec", mod: G711DEC, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 3}, groupId : 2,
- },
- {name: "vidtranscode_copy", mod: transcoder, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}
- },
- {name: "vidanalytics_copy", mod: analytics, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}
- },
- {name: "viddec1_copy", mod: VIDDEC1_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "viddec2back_copy", mod: VIDDEC2BACK_COPY, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}, groupId : 0,
- },
- {name: "universal_copy", mod: universal, threadAttrs: {
- stackMemId: 0, priority: Server.MINPRI + 1}
- }
- ];
- /*
- * We can use DMA in the VIDENC_COPY codecs.
- *
- * Note, these .useDMA config params are provided by specific codecs,
- * not all codecs are required to provide this level of flexibility
- * (and others will provide even more!)
- */
- VIDENC_COPY.useDMA = true;
- VIDENC1_COPY.alg.useDMA = false;
- /*
- * Note that we presume this server runs on a system with DSKT2 and DMAN3,
- * so we configure those modules here.
- */
- /*
- * ======== DSKT2 (xDAIS Alg. memory allocation) configuration ========
- *
- * DSKT2 is the memory manager for all algorithms running in the system,
- * granting them persistent and temporary ("scratch") internal and external
- * memory. We configure it here to define its memory allocation policy.
- *
- * DSKT2 settings are critical for algorithm performance.
- *
- * First we assign various types of algorithm internal memory (DARAM0..2,
- * SARAM0..2,IPROG, which are all the same on a C64+ DSP) to "L1DHEAP"
- * defined in the .tcf file as an internal memory heap. (For instance, if
- * an algorithm asks for 5K of DARAM1 memory, DSKT2 will allocate 5K from
- * L1DHEAP, if available, and give it to the algorithm; if the 5K is not
- * available in the L1DHEAP, that algorithm's creation will fail.)
- *
- * The remaining segments we point to the "DDRALGHEAP" external memory segment
- * (also defined in the.tcf) except for DSKT2_HEAP which stores DSKT2's
- * internal dynamically allocated objects, which must be preserved even if
- * no codec instances are running, so we place them in "DDR2" memory segment
- * with the rest of system code and static data.
- */
- var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
- DSKT2.DARAM0 = "L1DHEAP";
- DSKT2.DARAM1 = "L1DHEAP";
- DSKT2.DARAM2 = "L1DHEAP";
- DSKT2.SARAM0 = "L1DHEAP";
- DSKT2.SARAM1 = "L1DHEAP";
- DSKT2.SARAM2 = "L1DHEAP";
- DSKT2.ESDATA = "DDRALGHEAP";
- DSKT2.IPROG = "L1DHEAP";
- DSKT2.EPROG = "DDRALGHEAP";
- if (platform.match("evmOMAPL13[78]")) {
- DSKT2.DSKT2_HEAP = "SDRAM";
- }
- else {
- DSKT2.DSKT2_HEAP = "DDR2";
- }
- /*
- * Next we define how to fulfill algorithms' requests for fast ("scratch")
- * internal memory allocation; "scratch" is an area an algorithm writes to
- * while it processes a frame of data and
- *
- * First we turn off the switch that allows the DSKT2 algorithm memory manager
- * to give to an algorithm external memory for scratch if the system has run
- * out of internal memory. In that case, if an algorithm fails to get its
- * requested scratch memory, it will fail at creation rather than proceed to
- * run at poor performance. (If your algorithms fail to create, you may try
- * changing this value to "true" just to get it running and optimize other
- * scratch settings later.)
- *
- * Next we set "algorithm scratch sizes", a scheme we use to minimize internal
- * memory resources for algorithms' scratch memory allocation. Algorithms that
- * belong to the same "scratch group ID" -- field "groupId" in the algorithm's
- * Server.algs entry above, reflecting the priority of the task running the
- * algorithm -- don't run at the same time and thus can share the same
- * scratch area. When creating the first algorithm in a given "scratch group"
- * (between 0 and 19), a shared scratch area for that groupId is created with
- * a size equal to SARAM_SCRATCH_SIZES[<alg's groupId>] below -- unless the
- * algorithm requests more than that number, in which case the size will be
- * what the algorithm asks for. So SARAM_SCRATCH_SIZES[<alg's groupId>] size is
- * more of a groupId size guideline -- if the algorithm needs more it will get
- * it, but getting these size guidelines right is important for optimal use of
- * internal memory. The reason for this is that if an algorithm comes along
- * that needs more scratch memory than its groupId scratch area's size, it
- * will get that memory allocated separately, without sharing.
- *
- * This DSKT2.SARAM_SCRATCH_SIZES[<groupId>] does not mean it is a scratch size
- * that will be automatically allocated for the group <groupId> at system
- * startup, but only that is a preferred minimum scratch size to use for the
- * first algorithm that gets created in the <groupId> group, if any.
- *
- * (An example: if algorithms A and B with the same groupId = 0 require 10K and
- * 20K of scratch, and if SARAM_SCRATCH_SIZES[0] is 0, if A gets created first
- * DSKT2 allocates a shared scratch area for group 0 of size 10K, as A needs.
- * If then B gets to be created, the 20K scratch area it gets will not be
- * shared with A's -- or anyone else's; the total internal memory use will be
- * 30K. By contrast, if B gets created first, a 20K shared scratch will be
- * allocated, and when A comes along, it will get its 10K from the existing
- * group 0's 20K area. To eliminate such surprises, we set
- * SARAM_SCRATCH_SIZES[0] to 20K and always spend exactly 20K on A and B's
- * shared needs -- independent of their creation order. Not only do we save 10K
- * of precious internal memory, but we avoid the possibility that B can't be
- * created because less than 20K was available in the DSKT2 internal heaps.)
- *
- * In our example below, we set the size of groupId 0 to 32K -- as an example,
- * even though our codecs don't use it.
- *
- * Finally, note that if the codecs correctly implement the
- * ti.sdo.ce.ICodec.getDaramScratchSize() and .getSaramScratchSize() methods,
- * this scratch size configuration can be autogenerated by
- * configuring Server.autoGenScratchSizeArrays = true.
- */
- DSKT2.ALLOW_EXTERNAL_SCRATCH = true;
- //DSKT2.SARAM_SCRATCH_SIZES[0] = 32*1024;
- DSKT2.SARAM_SCRATCH_SIZES[0] = 64*1024;
- DSKT2.DARAM_SCRATCH_SIZES[0] = 64*1024;
- /*
- * ======== DMAN3 (DMA manager) configuration ========
- */
- var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');
- /* First we configure how DMAN3 handles memory allocations:
- *
- * Essentially the configuration below should work for most codec combinations.
- * If it doesn't work for yours -- meaning an algorithm fails to create due
- * to insufficient internal memory -- try the alternative (commented out
- * line that assigns "DDRALGHEAP" to DMAN3.heapInternal).
- *
- * What follows is an FYI -- an explanation for what the alternative would do:
- *
- * When we use an external memory segment (DDRALGHEAP) for DMAN3 internal
- * segment, we force algorithms to use external memory for what they think is
- * internal memory -- we do this in a memory-constrained environment
- * where all internal memory is used by cache and/or algorithm scratch
- * memory, pessimistically assuming that if DMAN3 uses any internal memory,
- * other components (algorithms) will not get the internal memory they need.
- *
- * This setting would affect performance very lightly.
- *
- * By setting DMAN3.heapInternal = <external-heap> DMAN3 *may not* supply
- * ACPY3_PROTOCOL IDMA3 channels the protocol required internal memory for
- * IDMA3 channel 'env' memory. To deal with this catch-22 situation we
- * configure DMAN3 with hook-functions to obtain internal-scratch memory
- * from the shared scratch pool for the associated algorithm's
- * scratch-group (i.e. it first tries to get the internal scratch memory
- * from DSKT2 shared allocation pool, hoping there is enough extra memory
- * in the shared pool, if that doesn't work it will try persistent
- * allocation from DMAN3.internalHeap).
- */
- DMAN3.heapInternal = "L1DHEAP"; /* L1DHEAP is an internal segment */
- // DMAN3.heapInternal = "DDRALGHEAP"; /* DDRALGHEAP is an external segment */
- DMAN3.heapExternal = "DDRALGHEAP";
- DMAN3.idma3Internal = false;
- DMAN3.scratchAllocFxn = "DSKT2_allocScratch";
- DMAN3.scratchFreeFxn = "DSKT2_freeScratch";
- /* Next, we configure all the physical resources that DMAN3 is granted
- * exclusively. These settings are optimized for the DSP on DM6446 (DaVinci).
- *
- * We assume PaRams 0..79 are taken by the Arm drivers, so we reserve
- * all the rest, up to 127 (there are 128 PaRam sets on DM6446).
- * DMAN3 takes TCC's 32 through 63 (hence the High TCC mask is 0xFFFFFFFF
- * and the Low TCC mask is 0). Of the 48 PaRams we reserved, we assign
- * all of them to scratch group 0; similarly, of the 32 TCCs we reserved,
- * we assign all of them to scratch group 0.
- *
- * If we had more scratch groups with algorithms that require EDMA, we would
- * split those 48 PaRams and 32 TCCs appropriately. For example, if we had
- * a video encoder alg. in group 0 and video decoder alg. in group 1, and they
- * both needed a number of EDMA channels, we could assing 24 PaRams and 16
- * TCCs to Groups [0] and [1] each. (Assuming both algorithms needed no more
- * than 24 channels to run properly.)
- */
- DMAN3.paRamBaseIndex = 80; // 1st EDMA3 PaRAM set available for DMAN3
- DMAN3.numQdmaChannels = 8; // number of device's QDMA channels to use
- DMAN3.qdmaChannels = [0,1,2,3,4,5,6,7]; // choice of QDMA channels to use
- DMAN3.numPaRamEntries = 48; // number of PaRAM sets exclusively used by DMAN
- DMAN3.numPaRamGroup[0] = 48; // number of PaRAM sets for scratch group 0
- DMAN3.numTccGroup[0] = 32; // number of TCCs assigned to scratch group 0
- if (platform.match("evmOMAPL13[78]")) {
- /* there are only 32 TCCs on OMAP-L137 and OMAP-L138 devices */
- DMAN3.tccAllocationMaskL = 0xffffffff; // which TCCs 0..31 for DMAN3
- DMAN3.tccAllocationMaskH = 0; // which TCCs 32..63 for DMAN3
- } else {
- /* there are 64 TCCs on all other supported devices */
- DMAN3.tccAllocationMaskL = 0; // which TCCs 0..31 for DMAN3
- DMAN3.tccAllocationMaskH = 0xffffffff; // which TCCs 32..63 for DMAN3
- }
- /* The remaining DMAN3 configuration settings are as defined in ti.sdo.fc.DMAN3
- * defaults. You may need to override them to add more QDMA channels and
- * configure per-scratch-group resource sub-allocations.
- */
- /*
- * ======== RMAN (IRES Resource manager) configuration ========
- */
- var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
- RMAN.useDSKT2 = true;
- RMAN.tableSize = 10;
- RMAN.semCreateFxn = "Sem_create";
- RMAN.semDeleteFxn = "Sem_delete";
- RMAN.semPendFxn = "Sem_pend";
- RMAN.semPostFxn = "Sem_post";
- /* The lock/unlock/set/getContext functions will default to DSKT2 */
- /*
- * @(#) ti.sdo.ce.examples.servers.all_codecs; 1, 0, 0,261; 12-2-2010 21:23:33; /db/atree/library/trees/ce/ce-r11x/src/ xlibrary
- */
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement