library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity circuito_combinado is
        port( EN : IN STD_LOGIC_VECTOR (0 TO 9);
              ENA: IN STD_LOGIC;
              DAT_B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              EQU,HIG,LES: OUT STD_LOGIC
        );



end circuito_combinado;


architecture Circuito of circuito_combinado is

COMPONENT comparador_4_bits
Port ( Dato_A : in  STD_LOGIC_VECTOR(3 DOWNTO 0);
       Dato_B : in  STD_LOGIC_VECTOR(3 DOWNTO 0);
       EQ,LE,HI : out  STD_LOGIC                                              -- EQ=IGUAL,LE=MENOR,HI=MAYOR;
                          );
end COMPONENT;


COMPONENT cod_prioritario
    Port ( E: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
           S: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
           ENABLE: IN STD_LOGIC);

end COMPONENT ;


SIGNAL SALIDA:STD_LOGIC_VECTOR(3 DOWNTO 0);     --Señal de interconexion entre el codificador y el comparador.

begin

CODIFICADOR:cod_prioritario PORT MAP (E=>EN,
                                      ENABLE=>ENA,
                                      S=>SALIDA);

COMPARADOR:comparador_4_bits PORT MAP  (Dato_A => SALIDA,
                                        Dato_B => DAT_B,
                                        EQ =>EQU,
                                        HI=>HIG,
                                        LE=>LES);


end Circuito;