---------- Begin Simulation Statistics ----------
sim_seconds                                  3.430266                       # Number of seconds simulated
sim_ticks                                3430265636000                       # Number of ticks simulated
final_tick                               3430265636000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1506478                       # Simulator instruction rate (inst/s)
host_op_rate                                  1665085                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2043777312                       # Simulator tick rate (ticks/s)
host_mem_usage                                 658320                       # Number of bytes of host memory used
host_seconds                                  1678.40                       # Real time elapsed on the host
sim_insts                                  2528465606                       # Number of instructions simulated
sim_ops                                    2794670189                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrls.bytes_read::cpu.inst           32896                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::cpu.data        22328640                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total           22361536                       # Number of bytes read from this memory
system.mem_ctrls.bytes_inst_read::cpu.inst        32896                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_inst_read::total         32896                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_written::writebacks       212480                       # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total          212480                       # Number of bytes written to this memory
system.mem_ctrls.num_reads::cpu.inst              514                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::cpu.data           348885                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total              349399                       # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::writebacks          3320                       # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total               3320                       # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::cpu.inst               9590                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::cpu.data            6509303                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total               6518893                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::cpu.inst          9590                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::total             9590                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::writebacks           61943                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total                61943                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::writebacks           61943                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu.inst              9590                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu.data           6509303                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total              6580836                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs                      349399                       # Number of read requests accepted
system.mem_ctrls.writeReqs                       3697                       # Number of write requests accepted
system.mem_ctrls.readBursts                    349399                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                     3697                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM               21944064                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                  417472                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                   27264                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                22361536                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys               236608                       # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ                   6523                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                  3248                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs       345420                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0                85                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1            219401                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2            116278                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3                54                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4                35                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5              3321                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6               108                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7                13                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8                51                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9                22                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10               28                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11               31                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12             3278                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13              108                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14               20                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15               43                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0                49                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1                 3                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2                 9                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3                30                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4                19                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5                40                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6                53                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7                10                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8                47                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9                 9                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10               18                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11               20                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12               17                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13               65                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14               14                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15               23                       # Per bank write bursts
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.totGap                  3430265630000                       # Total gap between requests
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                349399                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                 3697                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                  342876                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples       257171                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean     85.431219                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean    75.013017                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev    65.784795                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127       219426     85.32%     85.32% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255        24334      9.46%     94.79% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383         9016      3.51%     98.29% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511         3610      1.40%     99.69% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639          673      0.26%     99.96% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767           82      0.03%     99.99% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895           13      0.01%     99.99% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023            4      0.00%     99.99% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151           13      0.01%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total       257171                       # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples           26                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean   13187.269231                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean     38.371936                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev  67060.631382                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::0-16383           25     96.15%     96.15% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::327680-344063            1      3.85%    100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total            26                       # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples           26                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean      16.384615                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean     16.366545                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev      0.803837                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16               21     80.77%     80.77% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18                5     19.23%    100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total            26                       # Writes before turning the bus around for reads
system.mem_ctrls.totQLat                   6019478250                       # Total ticks spent queuing
system.mem_ctrls.totMemAccLat             12448403250                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat                 1714380000                       # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat                     17555.85                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                36305.85                       # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW                         6.40                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                         0.01                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                      6.52                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                      0.07                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         0.05                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     0.05                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                      20.00                       # Average write queue length when enqueuing
system.mem_ctrls.readRowHits                    85783                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                     342                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 25.02                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                76.17                       # Row buffer hit rate for writes
system.mem_ctrls.avgGap                    9714824.38                       # Average gap between requests
system.mem_ctrls.pageHitRate                    25.09                       # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy               1918607040                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy               1046859000                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy              2646352800                       # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy                1328400                       # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy         224048142240                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy         546290832330                       # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy         1578955821000                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy           2354907942810                       # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower            686.509275                       # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 2622206639250                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF  114544040000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT  693513319750                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls_1.actEnergy                 25567920                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy                 13950750                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy                27892800                       # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy                1328400                       # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy         224048142240                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy          82870623630                       # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy         1985464776000                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy           2292452281740                       # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower            668.302028                       # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 3303003961750                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF  114544040000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT   12715854500                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 3267                       # Number of system calls
system.cpu.numCycles                       6860531272                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  2528465606                       # Number of instructions committed
system.cpu.committedOps                    2794670189                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            2342223244                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                   159693629                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    399227840                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   2342223244                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads          4072281873                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1623561605                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads          10140794688                       # number of times the CC registers were read
system.cpu.num_cc_register_writes          1250916103                       # number of times the CC registers were written
system.cpu.num_mem_refs                     878404081                       # number of memory refs
system.cpu.num_load_insts                   532362476                       # Number of load instructions
system.cpu.num_store_insts                  346041605                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles               6860531271.998000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                         638761712                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                1916276002     68.57%     68.57% # Class of executed instruction
system.cpu.op_class::IntMult                       13      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::MemRead                532362476     19.05%     87.62% # Class of executed instruction
system.cpu.op_class::MemWrite               346041605     12.38%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 2794680096                       # Class of executed instruction
system.cpu.dcache.tags.replacements            348757                       # number of replacements
system.cpu.dcache.tags.tagsinuse           127.998068                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           878048570                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            348885                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs           2516.727776                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         679335000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   127.998068                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          128                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           49                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1757143795                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1757143795                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    478794377                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       478794377                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    292809327                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      292809327                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data     53222433                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total     53222433                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data     53222433                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total     53222433                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     771603704                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        771603704                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    771603704                       # number of overall hits
system.cpu.dcache.overall_hits::total       771603704                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       345571                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        345571                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         3314                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         3314                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       348885                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         348885                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       348885                       # number of overall misses
system.cpu.dcache.overall_misses::total        348885                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  23626120500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  23626120500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     75799500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     75799500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23701920000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23701920000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23701920000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23701920000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    479139948                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    479139948                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    292812641                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    292812641                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data     53222433                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total     53222433                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data     53222433                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total     53222433                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    771952589                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    771952589                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    771952589                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    771952589                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000721                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000721                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000011                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000011                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000452                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000452                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000452                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000452                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68368.354115                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68368.354115                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22872.510561                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 22872.510561                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67936.196741                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67936.196741                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67936.196741                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67936.196741                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         3320                       # number of writebacks
system.cpu.dcache.writebacks::total              3320                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       345571                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       345571                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3314                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         3314                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       348885                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       348885                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       348885                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       348885                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23280549500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23280549500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     72485500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     72485500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23353035000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23353035000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23353035000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23353035000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000721                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000721                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000452                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000452                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000452                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000452                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67368.354115                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67368.354115                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21872.510561                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21872.510561                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               386                       # number of replacements
system.cpu.icache.tags.tagsinuse           126.999624                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs          2528474907                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               514                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          4919211.881323                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      3430247933000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   126.999624                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992185                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992185                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          128                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            8                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        5056951356                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       5056951356                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst   2528474907                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      2528474907                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    2528474907                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       2528474907                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   2528474907                       # number of overall hits
system.cpu.icache.overall_hits::total      2528474907                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          514                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           514                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          514                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            514                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          514                       # number of overall misses
system.cpu.icache.overall_misses::total           514                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     29428000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     29428000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     29428000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     29428000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     29428000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     29428000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   2528475421                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   2528475421                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   2528475421                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   2528475421                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   2528475421                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   2528475421                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57252.918288                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 57252.918288                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 57252.918288                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 57252.918288                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 57252.918288                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 57252.918288                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks          386                       # number of writebacks
system.cpu.icache.writebacks::total               386                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          514                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          514                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          514                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          514                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          514                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          514                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28914000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     28914000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28914000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     28914000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28914000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     28914000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56252.918288                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56252.918288                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56252.918288                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 56252.918288                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56252.918288                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 56252.918288                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp             346085                       # Transaction distribution
system.membus.trans_dist::WritebackDirty         3320                       # Transaction distribution
system.membus.trans_dist::WritebackClean          377                       # Transaction distribution
system.membus.trans_dist::CleanEvict           345420                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3314                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3314                       # Transaction distribution
system.membus.trans_dist::ReadCleanReq            514                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        345571                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port         1405                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port      1046510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1047915                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port        57024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port     22541120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22598144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            698542                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  698542    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              698542                       # Request fanout histogram
system.membus.reqLayer0.occupancy           713372000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2727250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1911496500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
---------- Begin Simulation Statistics ----------
sim_seconds                                  3.430266                       # Number of seconds simulated
sim_ticks                                3430265636000                       # Number of ticks simulated
final_tick                               3430265636000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1506478                       # Simulator instruction rate (inst/s)
host_op_rate                                  1665085                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2043777312                       # Simulator tick rate (ticks/s)
host_mem_usage                                 658320                       # Number of bytes of host memory used
host_seconds                                  1678.40                       # Real time elapsed on the host
sim_insts                                  2528465606                       # Number of instructions simulated
sim_ops                                    2794670189                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrls.bytes_read::cpu.inst           32896                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::cpu.data        22328640                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total           22361536                       # Number of bytes read from this memory
system.mem_ctrls.bytes_inst_read::cpu.inst        32896                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_inst_read::total         32896                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_written::writebacks       212480                       # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total          212480                       # Number of bytes written to this memory
system.mem_ctrls.num_reads::cpu.inst              514                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::cpu.data           348885                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total              349399                       # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::writebacks          3320                       # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total               3320                       # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::cpu.inst               9590                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::cpu.data            6509303                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total               6518893                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::cpu.inst          9590                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::total             9590                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::writebacks           61943                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total                61943                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::writebacks           61943                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu.inst              9590                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu.data           6509303                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total              6580836                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs                      349399                       # Number of read requests accepted
system.mem_ctrls.writeReqs                       3697                       # Number of write requests accepted
system.mem_ctrls.readBursts                    349399                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                     3697                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM               21944064                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                  417472                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                   27264                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                22361536                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys               236608                       # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ                   6523                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                  3248                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs       345420                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0                85                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1            219401                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2            116278                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3                54                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4                35                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5              3321                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6               108                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7                13                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8                51                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9                22                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10               28                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11               31                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12             3278                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13              108                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14               20                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15               43                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0                49                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1                 3                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2                 9                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3                30                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4                19                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5                40                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6                53                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7                10                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8                47                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9                 9                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10               18                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11               20                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12               17                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13               65                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14               14                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15               23                       # Per bank write bursts
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.totGap                  3430265630000                       # Total gap between requests
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                349399                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                 3697                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                  342876                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                     27                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                     26                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples       257171                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean     85.431219                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean    75.013017                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev    65.784795                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127       219426     85.32%     85.32% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255        24334      9.46%     94.79% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383         9016      3.51%     98.29% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511         3610      1.40%     99.69% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639          673      0.26%     99.96% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767           82      0.03%     99.99% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895           13      0.01%     99.99% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023            4      0.00%     99.99% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151           13      0.01%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total       257171                       # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples           26                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean   13187.269231                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean     38.371936                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev  67060.631382                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::0-16383           25     96.15%     96.15% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::327680-344063            1      3.85%    100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total            26                       # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples           26                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean      16.384615                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean     16.366545                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev      0.803837                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16               21     80.77%     80.77% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18                5     19.23%    100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total            26                       # Writes before turning the bus around for reads
system.mem_ctrls.totQLat                   6019478250                       # Total ticks spent queuing
system.mem_ctrls.totMemAccLat             12448403250                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat                 1714380000                       # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat                     17555.85                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                36305.85                       # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW                         6.40                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                         0.01                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                      6.52                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                      0.07                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         0.05                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     0.05                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                      20.00                       # Average write queue length when enqueuing
system.mem_ctrls.readRowHits                    85783                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                     342                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 25.02                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                76.17                       # Row buffer hit rate for writes
system.mem_ctrls.avgGap                    9714824.38                       # Average gap between requests
system.mem_ctrls.pageHitRate                    25.09                       # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy               1918607040                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy               1046859000                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy              2646352800                       # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy                1328400                       # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy         224048142240                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy         546290832330                       # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy         1578955821000                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy           2354907942810                       # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower            686.509275                       # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 2622206639250                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF  114544040000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT  693513319750                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls_1.actEnergy                 25567920                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy                 13950750                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy                27892800                       # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy                1328400                       # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy         224048142240                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy          82870623630                       # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy         1985464776000                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy           2292452281740                       # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower            668.302028                       # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 3303003961750                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF  114544040000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT   12715854500                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 3267                       # Number of system calls
system.cpu.numCycles                       6860531272                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  2528465606                       # Number of instructions committed
system.cpu.committedOps                    2794670189                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            2342223244                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                   159693629                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    399227840                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   2342223244                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads          4072281873                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1623561605                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads          10140794688                       # number of times the CC registers were read
system.cpu.num_cc_register_writes          1250916103                       # number of times the CC registers were written
system.cpu.num_mem_refs                     878404081                       # number of memory refs
system.cpu.num_load_insts                   532362476                       # Number of load instructions
system.cpu.num_store_insts                  346041605                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles               6860531271.998000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                         638761712                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                1916276002     68.57%     68.57% # Class of executed instruction
system.cpu.op_class::IntMult                       13      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.57% # Class of executed instruction
system.cpu.op_class::MemRead                532362476     19.05%     87.62% # Class of executed instruction
system.cpu.op_class::MemWrite               346041605     12.38%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 2794680096                       # Class of executed instruction
system.cpu.dcache.tags.replacements            348757                       # number of replacements
system.cpu.dcache.tags.tagsinuse           127.998068                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           878048570                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            348885                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs           2516.727776                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         679335000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   127.998068                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          128                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           49                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1757143795                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1757143795                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    478794377                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       478794377                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    292809327                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      292809327                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data     53222433                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total     53222433                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data     53222433                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total     53222433                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     771603704                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        771603704                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    771603704                       # number of overall hits
system.cpu.dcache.overall_hits::total       771603704                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       345571                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        345571                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         3314                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         3314                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       348885                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         348885                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       348885                       # number of overall misses
system.cpu.dcache.overall_misses::total        348885                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  23626120500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  23626120500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     75799500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     75799500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23701920000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23701920000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23701920000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23701920000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    479139948                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    479139948                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    292812641                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    292812641                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data     53222433                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total     53222433                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data     53222433                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total     53222433                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    771952589                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    771952589                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    771952589                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    771952589                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000721                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000721                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000011                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000011                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000452                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000452                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000452                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000452                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68368.354115                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68368.354115                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22872.510561                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 22872.510561                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67936.196741                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67936.196741                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67936.196741                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67936.196741                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         3320                       # number of writebacks
system.cpu.dcache.writebacks::total              3320                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       345571                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       345571                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3314                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         3314                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       348885                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       348885                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       348885                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       348885                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23280549500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23280549500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     72485500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     72485500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23353035000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23353035000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23353035000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23353035000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000721                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000721                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000452                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000452                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000452                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000452                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67368.354115                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67368.354115                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21872.510561                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21872.510561                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66936.196741                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               386                       # number of replacements
system.cpu.icache.tags.tagsinuse           126.999624                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs          2528474907                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               514                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          4919211.881323                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      3430247933000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   126.999624                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992185                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992185                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          128                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            8                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        5056951356                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       5056951356                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst   2528474907                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      2528474907                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    2528474907                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       2528474907                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   2528474907                       # number of overall hits
system.cpu.icache.overall_hits::total      2528474907                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          514                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           514                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          514                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            514                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          514                       # number of overall misses
system.cpu.icache.overall_misses::total           514                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     29428000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     29428000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     29428000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     29428000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     29428000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     29428000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   2528475421                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   2528475421                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   2528475421                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   2528475421                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   2528475421                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   2528475421                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57252.918288                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 57252.918288                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 57252.918288                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 57252.918288                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 57252.918288                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 57252.918288                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks          386                       # number of writebacks
system.cpu.icache.writebacks::total               386                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          514                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          514                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          514                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          514                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          514                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          514                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28914000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     28914000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28914000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     28914000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28914000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     28914000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56252.918288                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56252.918288                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56252.918288                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 56252.918288                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56252.918288                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 56252.918288                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp             346085                       # Transaction distribution
system.membus.trans_dist::WritebackDirty         3320                       # Transaction distribution
system.membus.trans_dist::WritebackClean          377                       # Transaction distribution
system.membus.trans_dist::CleanEvict           345420                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3314                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3314                       # Transaction distribution
system.membus.trans_dist::ReadCleanReq            514                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        345571                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port         1405                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port      1046510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1047915                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port        57024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port     22541120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22598144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            698542                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  698542    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              698542                       # Request fanout histogram
system.membus.reqLayer0.occupancy           713372000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2727250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1911496500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------