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- [cpu]
- type = haswell
- numIQEntries = 64
- numROBEntries = 192
- LQEntries = 72
- SQEntries = 42
- [icache]
- hit_latency = 1
- response_latency = 1
- mshrs = 4
- tgts_per_mshr = 16
- size = 32kB
- assoc = 2
- is_top_level = true
- prefetch_on_access = true
- prefetcher = TaggedPrefetcher(degree = 2, latency = 1)
- [dcache]
- hit_latency = 3
- response_latency = 2
- mshrs = 16
- tgts_per_mshr = 16
- size = 32kB
- assoc = 4
- write_buffers = 16
- is_top_level = true
- prefetch_on_access = true
- prefetcher = StridePrefetcher(degree = 2, latency = 1)
- [l2]
- # 8 additional cycles on top of L1 miss
- hit_latency = 6
- response_latency = 2
- mshrs = 16
- tgts_per_mshr = 16
- size = 256kB
- assoc = 8
- write_buffers = 8
- prefetch_on_access = true
- prefetcher = StridePrefetcher(degree = 2, latency = 1)
- [l3]
- # 24 additional cycles on top of l2 miss
- hit_latency = 14
- response_latency = 10
- mshrs = 16
- tgts_per_mshr = 16
- size = 4MB
- assoc = 16
- write_buffers = 8
- prefetch_on_access = true
- prefetcher = StridePrefetcher(degree = 2, latency = 1)
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