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LLVM branching output 2017.01.19

upcFrost
Jan 19th, 2017
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  1. Args: ../llvm-build/bin/llc -march epiphany -mcpu E16 -O0 -filetype obj main.ll -o main.o -debug -asm-show-inst -print-after-all -mc-relax-all
  2.  
  3. Features:
  4. CPU:E16
  5.  
  6. *** IR Dump After Pre-ISel Intrinsic Lowering ***; ModuleID = 'main.ll'
  7. source_filename = "main.ll"
  8. target datalayout = "e-p:32:32-i8:8:16-i16:16-i64:64-f32:32-f64:64-n32-S64"
  9. target triple = "x86_64-pc-linux-gnu"
  10.  
  11. ; Function Attrs: nounwind uwtable
  12. define i32 @main() #0 {
  13. %1 = alloca i32, align 4
  14. %a = alloca i32, align 4
  15. store i32 0, i32* %1, align 4
  16. store i32 1, i32* %a, align 4
  17. %2 = load i32, i32* %a, align 4
  18. %3 = icmp sgt i32 %2, 3
  19. br i1 %3, label %4, label %5
  20.  
  21. ; <label>:4: ; preds = %0
  22. store i32 1, i32* %1, align 4
  23. br label %6
  24.  
  25. ; <label>:5: ; preds = %0
  26. store i32 0, i32* %1, align 4
  27. br label %6
  28.  
  29. ; <label>:6: ; preds = %5, %4
  30. %7 = load i32, i32* %1, align 4
  31. ret i32 %7
  32. }
  33.  
  34. attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="E16" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
  35.  
  36. !llvm.ident = !{!0}
  37.  
  38. !0 = !{!"clang version 3.8.0-2ubuntu4 (tags/RELEASE_380/final)"}
  39. *** IR Dump After Module Verifier ***
  40. ; Function Attrs: nounwind uwtable
  41. define i32 @main() #0 {
  42. %1 = alloca i32, align 4
  43. %a = alloca i32, align 4
  44. store i32 0, i32* %1, align 4
  45. store i32 1, i32* %a, align 4
  46. %2 = load i32, i32* %a, align 4
  47. %3 = icmp sgt i32 %2, 3
  48. br i1 %3, label %4, label %5
  49.  
  50. ; <label>:4: ; preds = %0
  51. store i32 1, i32* %1, align 4
  52. br label %6
  53.  
  54. ; <label>:5: ; preds = %0
  55. store i32 0, i32* %1, align 4
  56. br label %6
  57.  
  58. ; <label>:6: ; preds = %5, %4
  59. %7 = load i32, i32* %1, align 4
  60. ret i32 %7
  61. }
  62. *** IR Dump After Lower Garbage Collection Instructions ***
  63. ; Function Attrs: nounwind uwtable
  64. define i32 @main() #0 {
  65. %1 = alloca i32, align 4
  66. %a = alloca i32, align 4
  67. store i32 0, i32* %1, align 4
  68. store i32 1, i32* %a, align 4
  69. %2 = load i32, i32* %a, align 4
  70. %3 = icmp sgt i32 %2, 3
  71. br i1 %3, label %4, label %5
  72.  
  73. ; <label>:4: ; preds = %0
  74. store i32 1, i32* %1, align 4
  75. br label %6
  76.  
  77. ; <label>:5: ; preds = %0
  78. store i32 0, i32* %1, align 4
  79. br label %6
  80.  
  81. ; <label>:6: ; preds = %5, %4
  82. %7 = load i32, i32* %1, align 4
  83. ret i32 %7
  84. }
  85. *** IR Dump After Shadow Stack GC Lowering ***
  86. ; Function Attrs: nounwind uwtable
  87. define i32 @main() #0 {
  88. %1 = alloca i32, align 4
  89. %a = alloca i32, align 4
  90. store i32 0, i32* %1, align 4
  91. store i32 1, i32* %a, align 4
  92. %2 = load i32, i32* %a, align 4
  93. %3 = icmp sgt i32 %2, 3
  94. br i1 %3, label %4, label %5
  95.  
  96. ; <label>:4: ; preds = %0
  97. store i32 1, i32* %1, align 4
  98. br label %6
  99.  
  100. ; <label>:5: ; preds = %0
  101. store i32 0, i32* %1, align 4
  102. br label %6
  103.  
  104. ; <label>:6: ; preds = %5, %4
  105. %7 = load i32, i32* %1, align 4
  106. ret i32 %7
  107. }
  108. *** IR Dump After Remove unreachable blocks from the CFG ***
  109. ; Function Attrs: nounwind uwtable
  110. define i32 @main() #0 {
  111. %1 = alloca i32, align 4
  112. %a = alloca i32, align 4
  113. store i32 0, i32* %1, align 4
  114. store i32 1, i32* %a, align 4
  115. %2 = load i32, i32* %a, align 4
  116. %3 = icmp sgt i32 %2, 3
  117. br i1 %3, label %4, label %5
  118.  
  119. ; <label>:4: ; preds = %0
  120. store i32 1, i32* %1, align 4
  121. br label %6
  122.  
  123. ; <label>:5: ; preds = %0
  124. store i32 0, i32* %1, align 4
  125. br label %6
  126.  
  127. ; <label>:6: ; preds = %5, %4
  128. %7 = load i32, i32* %1, align 4
  129. ret i32 %7
  130. }
  131. *** IR Dump After Rewrite Symbols ***; ModuleID = 'main.ll'
  132. source_filename = "main.ll"
  133. target datalayout = "e-p:32:32-i8:8:16-i16:16-i64:64-f32:32-f64:64-n32-S64"
  134. target triple = "x86_64-pc-linux-gnu"
  135.  
  136. ; Function Attrs: nounwind uwtable
  137. define i32 @main() #0 {
  138. %1 = alloca i32, align 4
  139. %a = alloca i32, align 4
  140. store i32 0, i32* %1, align 4
  141. store i32 1, i32* %a, align 4
  142. %2 = load i32, i32* %a, align 4
  143. %3 = icmp sgt i32 %2, 3
  144. br i1 %3, label %4, label %5
  145.  
  146. ; <label>:4: ; preds = %0
  147. store i32 1, i32* %1, align 4
  148. br label %6
  149.  
  150. ; <label>:5: ; preds = %0
  151. store i32 0, i32* %1, align 4
  152. br label %6
  153.  
  154. ; <label>:6: ; preds = %5, %4
  155. %7 = load i32, i32* %1, align 4
  156. ret i32 %7
  157. }
  158.  
  159. attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="E16" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
  160.  
  161. !llvm.ident = !{!0}
  162.  
  163. !0 = !{!"clang version 3.8.0-2ubuntu4 (tags/RELEASE_380/final)"}
  164. *** IR Dump After Exception handling preparation ***
  165. ; Function Attrs: nounwind uwtable
  166. define i32 @main() #0 {
  167. %1 = alloca i32, align 4
  168. %a = alloca i32, align 4
  169. store i32 0, i32* %1, align 4
  170. store i32 1, i32* %a, align 4
  171. %2 = load i32, i32* %a, align 4
  172. %3 = icmp sgt i32 %2, 3
  173. br i1 %3, label %4, label %5
  174.  
  175. ; <label>:4: ; preds = %0
  176. store i32 1, i32* %1, align 4
  177. br label %6
  178.  
  179. ; <label>:5: ; preds = %0
  180. store i32 0, i32* %1, align 4
  181. br label %6
  182.  
  183. ; <label>:6: ; preds = %5, %4
  184. %7 = load i32, i32* %1, align 4
  185. ret i32 %7
  186. }
  187. [SafeStack] Function: main
  188. [SafeStack] safestack is not requested for this function
  189. *** IR Dump After Safe Stack instrumentation pass ***
  190. ; Function Attrs: nounwind uwtable
  191. define i32 @main() #0 {
  192. %1 = alloca i32, align 4
  193. %a = alloca i32, align 4
  194. store i32 0, i32* %1, align 4
  195. store i32 1, i32* %a, align 4
  196. %2 = load i32, i32* %a, align 4
  197. %3 = icmp sgt i32 %2, 3
  198. br i1 %3, label %4, label %5
  199.  
  200. ; <label>:4: ; preds = %0
  201. store i32 1, i32* %1, align 4
  202. br label %6
  203.  
  204. ; <label>:5: ; preds = %0
  205. store i32 0, i32* %1, align 4
  206. br label %6
  207.  
  208. ; <label>:6: ; preds = %5, %4
  209. %7 = load i32, i32* %1, align 4
  210. ret i32 %7
  211. }
  212. *** IR Dump After Module Verifier ***
  213. ; Function Attrs: nounwind uwtable
  214. define i32 @main() #0 {
  215. %1 = alloca i32, align 4
  216. %a = alloca i32, align 4
  217. store i32 0, i32* %1, align 4
  218. store i32 1, i32* %a, align 4
  219. %2 = load i32, i32* %a, align 4
  220. %3 = icmp sgt i32 %2, 3
  221. br i1 %3, label %4, label %5
  222.  
  223. ; <label>:4: ; preds = %0
  224. store i32 1, i32* %1, align 4
  225. br label %6
  226.  
  227. ; <label>:5: ; preds = %0
  228. store i32 0, i32* %1, align 4
  229. br label %6
  230.  
  231. ; <label>:6: ; preds = %5, %4
  232. %7 = load i32, i32* %1, align 4
  233. ret i32 %7
  234. }
  235.  
  236.  
  237.  
  238. === main
  239. Initial selection DAG: BB#0 'main:'
  240. SelectionDAG has 18 nodes:
  241. t0: ch = EntryToken
  242. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  243. t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  244. t8: i32,ch = load<LD4[%a]> t7, FrameIndex:i32<1>, undef:i32
  245. t11: i1 = setcc t8, Constant:i32<3>, setgt:ch
  246. t13: i1 = xor t11, Constant:i1<-1>
  247. t15: ch = brcond t7, t13, BasicBlock:ch< 0x3c68c68>
  248. t17: ch = br t15, BasicBlock:ch< 0x3c68bb8>
  249.  
  250.  
  251.  
  252. Combining: t17: ch = br t15, BasicBlock:ch< 0x3c68bb8>
  253.  
  254. Combining: t16: ch = BasicBlock< 0x3c68bb8>
  255.  
  256. Combining: t15: ch = brcond t7, t13, BasicBlock:ch< 0x3c68c68>
  257.  
  258. Combining: t14: ch = BasicBlock< 0x3c68c68>
  259.  
  260. Combining: t13: i1 = xor t11, Constant:i1<-1>
  261. ... into: t19: i1 = setcc t8, Constant:i32<3>, setle:ch
  262.  
  263. Combining: t15: ch = brcond t7, t19, BasicBlock:ch< 0x3c68c68>
  264. ... into: t20: ch = br_cc t7, setle:ch, t8, Constant:i32<3>, BasicBlock:ch< 0x3c68c68>
  265.  
  266. Combining: t18: ch = setle
  267.  
  268. Combining: t14: ch = BasicBlock< 0x3c68c68>
  269.  
  270. Combining: t17: ch = br t20, BasicBlock:ch< 0x3c68bb8>
  271.  
  272. Combining: t20: ch = br_cc t7, setle:ch, t8, Constant:i32<3>, BasicBlock:ch< 0x3c68c68>
  273. ... into: t24: ch = br_cc t7, setlt:ch, t8, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  274.  
  275. Combining: t14: ch = BasicBlock< 0x3c68c68>
  276.  
  277. Combining: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  278.  
  279. Combining: t24: ch = br_cc t7, setlt:ch, t8, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  280.  
  281. Combining: t21: i32 = Constant<4>
  282.  
  283. Combining: t22: ch = setlt
  284.  
  285. Combining: t21: i32 = Constant<4>
  286.  
  287. Combining: t22: ch = setlt
  288.  
  289. Combining: t8: i32,ch = load<LD4[%a]> t7, FrameIndex:i32<1>, undef:i32
  290.  
  291. Replacing.1 t8: i32,ch = load<LD4[%a]> t7, FrameIndex:i32<1>, undef:i32
  292.  
  293. With: t5: i32 = Constant<1>
  294. and 1 other values
  295.  
  296. Combining: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  297.  
  298. Combining: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  299.  
  300. Combining: t6: i32 = FrameIndex<1>
  301.  
  302. Combining: t5: i32 = Constant<1>
  303.  
  304. Combining: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  305.  
  306. Combining: t3: i32 = undef
  307.  
  308. Combining: t2: i32 = FrameIndex<0>
  309.  
  310. Combining: t1: i32 = Constant<0>
  311.  
  312. Combining: t0: ch = EntryToken
  313. Optimized lowered selection DAG: BB#0 'main:'
  314. SelectionDAG has 14 nodes:
  315. t0: ch = EntryToken
  316. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  317. t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  318. t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  319. t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  320.  
  321.  
  322. Legally typed node: t22: ch = setlt
  323.  
  324. Legally typed node: t21: i32 = Constant<4>
  325.  
  326. Legally typed node: t16: ch = BasicBlock< 0x3c68bb8>
  327.  
  328. Legally typed node: t14: ch = BasicBlock< 0x3c68c68>
  329.  
  330. Legally typed node: t6: i32 = FrameIndex<1>
  331.  
  332. Legally typed node: t5: i32 = Constant<1>
  333.  
  334. Legally typed node: t3: i32 = undef
  335.  
  336. Legally typed node: t2: i32 = FrameIndex<0>
  337.  
  338. Legally typed node: t1: i32 = Constant<0>
  339.  
  340. Legally typed node: t0: ch = EntryToken
  341.  
  342. Legally typed node: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  343.  
  344. Legally typed node: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  345.  
  346. Legally typed node: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  347.  
  348. Legally typed node: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  349.  
  350. Legally typed node: t65535: ch = handlenode t17
  351.  
  352. Type-legalized selection DAG: BB#0 'main:'
  353. SelectionDAG has 14 nodes:
  354. t0: ch = EntryToken
  355. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  356. t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  357. t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  358. t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  359.  
  360.  
  361.  
  362. Legalizing: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  363.  
  364. Legalizing: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  365.  
  366. Legalizing: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  367.  
  368. Legalizing: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  369.  
  370. Legalizing: t22: ch = setlt
  371.  
  372. Legalizing: t21: i32 = Constant<4>
  373.  
  374. Legalizing: t16: ch = BasicBlock< 0x3c68bb8>
  375.  
  376. Legalizing: t14: ch = BasicBlock< 0x3c68c68>
  377.  
  378. Legalizing: t6: i32 = FrameIndex<1>
  379.  
  380. Legalizing: t5: i32 = Constant<1>
  381.  
  382. Legalizing: t3: i32 = undef
  383.  
  384. Legalizing: t2: i32 = FrameIndex<0>
  385.  
  386. Legalizing: t1: i32 = Constant<0>
  387.  
  388. Legalizing: t0: ch = EntryToken
  389. Legalized selection DAG: BB#0 'main:'
  390. SelectionDAG has 14 nodes:
  391. t0: ch = EntryToken
  392. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  393. t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  394. t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  395. t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  396.  
  397.  
  398.  
  399. Legalizing: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  400.  
  401. Combining: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  402.  
  403. Legalizing: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  404.  
  405. Combining: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  406.  
  407. Legalizing: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  408.  
  409. Combining: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  410.  
  411. Legalizing: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  412.  
  413. Combining: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  414.  
  415. Legalizing: t22: ch = setlt
  416.  
  417. Combining: t22: ch = setlt
  418.  
  419. Legalizing: t21: i32 = Constant<4>
  420.  
  421. Combining: t21: i32 = Constant<4>
  422.  
  423. Legalizing: t16: ch = BasicBlock< 0x3c68bb8>
  424.  
  425. Combining: t16: ch = BasicBlock< 0x3c68bb8>
  426.  
  427. Legalizing: t14: ch = BasicBlock< 0x3c68c68>
  428.  
  429. Combining: t14: ch = BasicBlock< 0x3c68c68>
  430.  
  431. Legalizing: t6: i32 = FrameIndex<1>
  432.  
  433. Combining: t6: i32 = FrameIndex<1>
  434.  
  435. Legalizing: t5: i32 = Constant<1>
  436.  
  437. Combining: t5: i32 = Constant<1>
  438.  
  439. Legalizing: t3: i32 = undef
  440.  
  441. Combining: t3: i32 = undef
  442.  
  443. Legalizing: t2: i32 = FrameIndex<0>
  444.  
  445. Combining: t2: i32 = FrameIndex<0>
  446.  
  447. Legalizing: t1: i32 = Constant<0>
  448.  
  449. Combining: t1: i32 = Constant<0>
  450.  
  451. Legalizing: t0: ch = EntryToken
  452.  
  453. Combining: t0: ch = EntryToken
  454. Optimized legalized selection DAG: BB#0 'main:'
  455. SelectionDAG has 14 nodes:
  456. t0: ch = EntryToken
  457. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  458. t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  459. t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  460. t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  461.  
  462.  
  463. ===== Instruction selection begins: BB#0 ''
  464. Selecting: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  465.  
  466. ISEL: Starting pattern match on root node: t17: ch = br t24, BasicBlock:ch< 0x3c68bb8>
  467.  
  468. Morphed node: t17: ch = BNONE32 BasicBlock:ch< 0x3c68bb8>, t24
  469.  
  470. ISEL: Match complete!
  471. Selecting: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  472.  
  473. ISEL: Starting pattern match on root node: t24: ch = br_cc t7, setlt:ch, Constant:i32<1>, Constant:i32<4>, BasicBlock:ch< 0x3c68c68>
  474.  
  475. Initial Opcode index to 1299
  476. Skipped scope entry (due to false predicate) at index 1303, continuing at 1333
  477. Skipped scope entry (due to false predicate) at index 1334, continuing at 1364
  478. Skipped scope entry (due to false predicate) at index 1365, continuing at 1395
  479. Skipped scope entry (due to false predicate) at index 1396, continuing at 1426
  480. Skipped scope entry (due to false predicate) at index 1427, continuing at 1457
  481. Skipped scope entry (due to false predicate) at index 1458, continuing at 1488
  482. Skipped scope entry (due to false predicate) at index 1489, continuing at 1519
  483. Created node: t27: i32,i32 = SUBrr_r32 Constant:i32<1>, Constant:i32<4>
  484.  
  485. Morphed node: t24: ch = BLT32 t27, BasicBlock:ch< 0x3c68c68>, t7
  486.  
  487. ISEL: Match complete!
  488. Selecting: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  489.  
  490. ISEL: Starting pattern match on root node: t7: ch = store<ST4[%a]> t4, Constant:i32<1>, FrameIndex:i32<1>, undef:i32
  491.  
  492. Initial Opcode index to 336
  493. Skipped scope entry (due to false predicate) at index 348, continuing at 418
  494. Match failed at index 425
  495. Continuing at 437
  496. Morphed node: t7: ch = STRi32_r32<Mem:ST4[%a]> Constant:i32<1>, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  497.  
  498. ISEL: Match complete!
  499. Selecting: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  500.  
  501. ISEL: Starting pattern match on root node: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  502.  
  503. Initial Opcode index to 336
  504. Skipped scope entry (due to false predicate) at index 348, continuing at 418
  505. Match failed at index 425
  506. Continuing at 437
  507. Morphed node: t4: ch = STRi32_r32<Mem:ST4[%1]> Constant:i32<0>, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  508.  
  509. ISEL: Match complete!
  510. Selecting: t21: i32 = Constant<4>
  511.  
  512. ISEL: Starting pattern match on root node: t21: i32 = Constant<4>
  513.  
  514. Initial Opcode index to 929
  515. Morphed node: t21: i32 = MOVi16ri TargetConstant:i32<4>
  516.  
  517. ISEL: Match complete!
  518. Selecting: t16: ch = BasicBlock< 0x3c68bb8>
  519.  
  520. Selecting: t14: ch = BasicBlock< 0x3c68c68>
  521.  
  522. Selecting: t5: i32 = Constant<1>
  523.  
  524. ISEL: Starting pattern match on root node: t5: i32 = Constant<1>
  525.  
  526. Initial Opcode index to 929
  527. Morphed node: t5: i32 = MOVi16ri TargetConstant:i32<1>
  528.  
  529. ISEL: Match complete!
  530. Selecting: t1: i32 = Constant<0>
  531.  
  532. ISEL: Starting pattern match on root node: t1: i32 = Constant<0>
  533.  
  534. Initial Opcode index to 929
  535. Morphed node: t1: i32 = MOVi16ri TargetConstant:i32<0>
  536.  
  537. ISEL: Match complete!
  538. Selecting: t0: ch = EntryToken
  539.  
  540. ===== Instruction selection ends:
  541. Selected selection DAG: BB#0 'main:'
  542. SelectionDAG has 16 nodes:
  543. t5: i32 = MOVi16ri TargetConstant:i32<1>
  544. t21: i32 = MOVi16ri TargetConstant:i32<4>
  545. t27: i32,i32 = SUBrr_r32 t5, t21
  546. t1: i32 = MOVi16ri TargetConstant:i32<0>
  547. t0: ch = EntryToken
  548. t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  549. t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  550. t24: ch = BLT32 t27, BasicBlock:ch< 0x3c68c68>, t7
  551. t17: ch = BNONE32 BasicBlock:ch< 0x3c68bb8>, t24
  552.  
  553.  
  554. ********** List Scheduling BB#0 '' **********
  555. SU(0): t17: ch = BNONE32 BasicBlock:ch< 0x3c68bb8>, t24
  556.  
  557. # preds left : 1
  558. # succs left : 0
  559. # rdefs left : 0
  560. Latency : 1
  561. Depth : 4
  562. Height : 0
  563. Predecessors:
  564. ch SU(1): Latency=1
  565. SU(1): t24: ch = BLT32 t27, BasicBlock:ch< 0x3c68c68>, t7
  566.  
  567. # preds left : 2
  568. # succs left : 1
  569. # rdefs left : 0
  570. Latency : 1
  571. Depth : 3
  572. Height : 1
  573. Predecessors:
  574. val SU(6): Latency=1
  575. ch SU(2): Latency=1
  576. Successors:
  577. ch SU(0): Latency=1
  578. SU(2): t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  579.  
  580. # preds left : 2
  581. # succs left : 1
  582. # rdefs left : 0
  583. Latency : 1
  584. Depth : 2
  585. Height : 2
  586. Predecessors:
  587. val SU(5): Latency=1
  588. ch SU(3): Latency=1
  589. Successors:
  590. ch SU(1): Latency=1
  591. SU(3): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  592.  
  593. # preds left : 1
  594. # succs left : 1
  595. # rdefs left : 0
  596. Latency : 1
  597. Depth : 1
  598. Height : 3
  599. Predecessors:
  600. val SU(4): Latency=1
  601. Successors:
  602. ch SU(2): Latency=1
  603. SU(4): t1: i32 = MOVi16ri TargetConstant:i32<0>
  604.  
  605. # preds left : 0
  606. # succs left : 1
  607. # rdefs left : 1
  608. Latency : 1
  609. Depth : 0
  610. Height : 4
  611. Successors:
  612. val SU(3): Latency=1
  613. SU(5): t5: i32 = MOVi16ri TargetConstant:i32<1>
  614.  
  615. # preds left : 0
  616. # succs left : 2
  617. # rdefs left : 1
  618. Latency : 1
  619. Depth : 0
  620. Height : 3
  621. Successors:
  622. val SU(2): Latency=1
  623. val SU(6): Latency=1
  624. SU(6): t27: i32,i32 = SUBrr_r32 t5, t21
  625.  
  626. # preds left : 2
  627. # succs left : 1
  628. # rdefs left : 1
  629. Latency : 1
  630. Depth : 1
  631. Height : 2
  632. Predecessors:
  633. val SU(5): Latency=1
  634. val SU(7): Latency=1
  635. Successors:
  636. val SU(1): Latency=1
  637. SU(7): t21: i32 = MOVi16ri TargetConstant:i32<4>
  638.  
  639. # preds left : 0
  640. # succs left : 1
  641. # rdefs left : 1
  642. Latency : 1
  643. Depth : 0
  644. Height : 3
  645. Successors:
  646. val SU(6): Latency=1
  647.  
  648. Examining Available:
  649. Height 0: SU(0): t17: ch = BNONE32 BasicBlock:ch< 0x3c68bb8>, t24
  650.  
  651.  
  652. *** Scheduling [0]: SU(0): t17: ch = BNONE32 BasicBlock:ch< 0x3c68bb8>, t24
  653.  
  654.  
  655. Examining Available:
  656. Height 1: SU(1): t24: ch = BLT32 t27, BasicBlock:ch< 0x3c68c68>, t7
  657.  
  658.  
  659. *** Scheduling [1]: SU(1): t24: ch = BLT32 t27, BasicBlock:ch< 0x3c68c68>, t7
  660.  
  661.  
  662. Examining Available:
  663. Height 2: SU(6): t27: i32,i32 = SUBrr_r32 t5, t21
  664.  
  665. Height 2: SU(2): t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  666.  
  667.  
  668. *** Scheduling [2]: SU(6): t27: i32,i32 = SUBrr_r32 t5, t21
  669.  
  670.  
  671. Examining Available:
  672. Height 3: SU(7): t21: i32 = MOVi16ri TargetConstant:i32<4>
  673.  
  674. Height 2: SU(2): t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  675.  
  676.  
  677. *** Scheduling [3]: SU(7): t21: i32 = MOVi16ri TargetConstant:i32<4>
  678.  
  679.  
  680. Examining Available:
  681. Height 2: SU(2): t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  682.  
  683.  
  684. *** Scheduling [4]: SU(2): t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  685.  
  686.  
  687. Examining Available:
  688. Height 5: SU(5): t5: i32 = MOVi16ri TargetConstant:i32<1>
  689.  
  690. Height 5: SU(3): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  691.  
  692.  
  693. *** Scheduling [5]: SU(5): t5: i32 = MOVi16ri TargetConstant:i32<1>
  694.  
  695.  
  696. Examining Available:
  697. Height 5: SU(3): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  698.  
  699.  
  700. *** Scheduling [6]: SU(3): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  701.  
  702.  
  703. Examining Available:
  704. Height 7: SU(4): t1: i32 = MOVi16ri TargetConstant:i32<0>
  705.  
  706.  
  707. *** Scheduling [7]: SU(4): t1: i32 = MOVi16ri TargetConstant:i32<0>
  708.  
  709. *** Final schedule ***
  710. SU(4): t1: i32 = MOVi16ri TargetConstant:i32<0>
  711.  
  712. SU(3): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  713.  
  714. SU(5): t5: i32 = MOVi16ri TargetConstant:i32<1>
  715.  
  716. SU(2): t7: ch = STRi32_r32<Mem:ST4[%a]> t5, TargetFrameIndex:i32<1>, TargetConstant:i32<0>, t4
  717.  
  718. SU(7): t21: i32 = MOVi16ri TargetConstant:i32<4>
  719.  
  720. SU(6): t27: i32,i32 = SUBrr_r32 t5, t21
  721.  
  722. SU(1): t24: ch = BLT32 t27, BasicBlock:ch< 0x3c68c68>, t7
  723.  
  724. SU(0): t17: ch = BNONE32 BasicBlock:ch< 0x3c68bb8>, t24
  725.  
  726.  
  727. Total amount of phi nodes to update: 0
  728. Initial selection DAG: BB#2 'main:'
  729. SelectionDAG has 7 nodes:
  730. t0: ch = EntryToken
  731. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  732. t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  733.  
  734.  
  735.  
  736. Combining: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  737.  
  738. Combining: t5: ch = BasicBlock< 0x3c68d18>
  739.  
  740. Combining: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  741.  
  742. Combining: t3: i32 = undef
  743.  
  744. Combining: t2: i32 = FrameIndex<0>
  745.  
  746. Combining: t1: i32 = Constant<0>
  747.  
  748. Combining: t0: ch = EntryToken
  749. Optimized lowered selection DAG: BB#2 'main:'
  750. SelectionDAG has 7 nodes:
  751. t0: ch = EntryToken
  752. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  753. t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  754.  
  755.  
  756. Legally typed node: t5: ch = BasicBlock< 0x3c68d18>
  757.  
  758. Legally typed node: t3: i32 = undef
  759.  
  760. Legally typed node: t2: i32 = FrameIndex<0>
  761.  
  762. Legally typed node: t1: i32 = Constant<0>
  763.  
  764. Legally typed node: t0: ch = EntryToken
  765.  
  766. Legally typed node: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  767.  
  768. Legally typed node: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  769.  
  770. Legally typed node: t65535: ch = handlenode t6
  771.  
  772. Type-legalized selection DAG: BB#2 'main:'
  773. SelectionDAG has 7 nodes:
  774. t0: ch = EntryToken
  775. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  776. t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  777.  
  778.  
  779.  
  780. Legalizing: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  781.  
  782. Legalizing: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  783.  
  784. Legalizing: t5: ch = BasicBlock< 0x3c68d18>
  785.  
  786. Legalizing: t3: i32 = undef
  787.  
  788. Legalizing: t2: i32 = FrameIndex<0>
  789.  
  790. Legalizing: t1: i32 = Constant<0>
  791.  
  792. Legalizing: t0: ch = EntryToken
  793. Legalized selection DAG: BB#2 'main:'
  794. SelectionDAG has 7 nodes:
  795. t0: ch = EntryToken
  796. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  797. t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  798.  
  799.  
  800.  
  801. Legalizing: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  802.  
  803. Combining: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  804.  
  805. Legalizing: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  806.  
  807. Combining: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  808.  
  809. Legalizing: t5: ch = BasicBlock< 0x3c68d18>
  810.  
  811. Combining: t5: ch = BasicBlock< 0x3c68d18>
  812.  
  813. Legalizing: t3: i32 = undef
  814.  
  815. Combining: t3: i32 = undef
  816.  
  817. Legalizing: t2: i32 = FrameIndex<0>
  818.  
  819. Combining: t2: i32 = FrameIndex<0>
  820.  
  821. Legalizing: t1: i32 = Constant<0>
  822.  
  823. Combining: t1: i32 = Constant<0>
  824.  
  825. Legalizing: t0: ch = EntryToken
  826.  
  827. Combining: t0: ch = EntryToken
  828. Optimized legalized selection DAG: BB#2 'main:'
  829. SelectionDAG has 7 nodes:
  830. t0: ch = EntryToken
  831. t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  832. t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  833.  
  834.  
  835. ===== Instruction selection begins: BB#2 ''
  836. Selecting: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  837.  
  838. ISEL: Starting pattern match on root node: t6: ch = br t4, BasicBlock:ch< 0x3c68d18>
  839.  
  840. Initial Opcode index to 1281
  841. Morphed node: t6: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t4
  842.  
  843. ISEL: Match complete!
  844. Selecting: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  845.  
  846. ISEL: Starting pattern match on root node: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
  847.  
  848. Initial Opcode index to 336
  849. Skipped scope entry (due to false predicate) at index 348, continuing at 418
  850. Match failed at index 425
  851. Continuing at 437
  852. Morphed node: t4: ch = STRi32_r32<Mem:ST4[%1]> Constant:i32<0>, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  853.  
  854. ISEL: Match complete!
  855. Selecting: t5: ch = BasicBlock< 0x3c68d18>
  856.  
  857. Selecting: t1: i32 = Constant<0>
  858.  
  859. ISEL: Starting pattern match on root node: t1: i32 = Constant<0>
  860.  
  861. Initial Opcode index to 929
  862. Morphed node: t1: i32 = MOVi16ri TargetConstant:i32<0>
  863.  
  864. ISEL: Match complete!
  865. Selecting: t0: ch = EntryToken
  866.  
  867. ===== Instruction selection ends:
  868. Selected selection DAG: BB#2 'main:'
  869. SelectionDAG has 7 nodes:
  870. t1: i32 = MOVi16ri TargetConstant:i32<0>
  871. t0: ch = EntryToken
  872. t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  873. t6: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t4
  874.  
  875.  
  876. ********** List Scheduling BB#2 '' **********
  877. SU(0): t6: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t4
  878.  
  879. # preds left : 1
  880. # succs left : 0
  881. # rdefs left : 0
  882. Latency : 1
  883. Depth : 2
  884. Height : 0
  885. Predecessors:
  886. ch SU(1): Latency=1
  887. SU(1): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  888.  
  889. # preds left : 1
  890. # succs left : 1
  891. # rdefs left : 0
  892. Latency : 1
  893. Depth : 1
  894. Height : 1
  895. Predecessors:
  896. val SU(2): Latency=1
  897. Successors:
  898. ch SU(0): Latency=1
  899. SU(2): t1: i32 = MOVi16ri TargetConstant:i32<0>
  900.  
  901. # preds left : 0
  902. # succs left : 1
  903. # rdefs left : 1
  904. Latency : 1
  905. Depth : 0
  906. Height : 2
  907. Successors:
  908. val SU(1): Latency=1
  909.  
  910. Examining Available:
  911. Height 0: SU(0): t6: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t4
  912.  
  913.  
  914. *** Scheduling [0]: SU(0): t6: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t4
  915.  
  916.  
  917. Examining Available:
  918. Height 1: SU(1): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  919.  
  920.  
  921. *** Scheduling [1]: SU(1): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  922.  
  923.  
  924. Examining Available:
  925. Height 2: SU(2): t1: i32 = MOVi16ri TargetConstant:i32<0>
  926.  
  927.  
  928. *** Scheduling [2]: SU(2): t1: i32 = MOVi16ri TargetConstant:i32<0>
  929.  
  930. *** Final schedule ***
  931. SU(2): t1: i32 = MOVi16ri TargetConstant:i32<0>
  932.  
  933. SU(1): t4: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  934.  
  935. SU(0): t6: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t4
  936.  
  937.  
  938. Total amount of phi nodes to update: 0
  939. Initial selection DAG: BB#1 'main:'
  940. SelectionDAG has 8 nodes:
  941. t3: i32 = Constant<0>
  942. t0: ch = EntryToken
  943. t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  944. t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  945.  
  946.  
  947.  
  948. Combining: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  949.  
  950. Combining: t6: ch = BasicBlock< 0x3c68d18>
  951.  
  952. Combining: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  953.  
  954. Combining: t4: i32 = undef
  955.  
  956. Combining: t2: i32 = FrameIndex<0>
  957.  
  958. Combining: t1: i32 = Constant<1>
  959.  
  960. Combining: t0: ch = EntryToken
  961. Optimized lowered selection DAG: BB#1 'main:'
  962. SelectionDAG has 7 nodes:
  963. t0: ch = EntryToken
  964. t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  965. t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  966.  
  967.  
  968. Legally typed node: t6: ch = BasicBlock< 0x3c68d18>
  969.  
  970. Legally typed node: t4: i32 = undef
  971.  
  972. Legally typed node: t2: i32 = FrameIndex<0>
  973.  
  974. Legally typed node: t1: i32 = Constant<1>
  975.  
  976. Legally typed node: t0: ch = EntryToken
  977.  
  978. Legally typed node: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  979.  
  980. Legally typed node: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  981.  
  982. Legally typed node: t65535: ch = handlenode t7
  983.  
  984. Type-legalized selection DAG: BB#1 'main:'
  985. SelectionDAG has 7 nodes:
  986. t0: ch = EntryToken
  987. t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  988. t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  989.  
  990.  
  991.  
  992. Legalizing: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  993.  
  994. Legalizing: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  995.  
  996. Legalizing: t6: ch = BasicBlock< 0x3c68d18>
  997.  
  998. Legalizing: t4: i32 = undef
  999.  
  1000. Legalizing: t2: i32 = FrameIndex<0>
  1001.  
  1002. Legalizing: t1: i32 = Constant<1>
  1003.  
  1004. Legalizing: t0: ch = EntryToken
  1005. Legalized selection DAG: BB#1 'main:'
  1006. SelectionDAG has 7 nodes:
  1007. t0: ch = EntryToken
  1008. t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  1009. t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  1010.  
  1011.  
  1012.  
  1013. Legalizing: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  1014.  
  1015. Combining: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  1016.  
  1017. Legalizing: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  1018.  
  1019. Combining: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  1020.  
  1021. Legalizing: t6: ch = BasicBlock< 0x3c68d18>
  1022.  
  1023. Combining: t6: ch = BasicBlock< 0x3c68d18>
  1024.  
  1025. Legalizing: t4: i32 = undef
  1026.  
  1027. Combining: t4: i32 = undef
  1028.  
  1029. Legalizing: t2: i32 = FrameIndex<0>
  1030.  
  1031. Combining: t2: i32 = FrameIndex<0>
  1032.  
  1033. Legalizing: t1: i32 = Constant<1>
  1034.  
  1035. Combining: t1: i32 = Constant<1>
  1036.  
  1037. Legalizing: t0: ch = EntryToken
  1038.  
  1039. Combining: t0: ch = EntryToken
  1040. Optimized legalized selection DAG: BB#1 'main:'
  1041. SelectionDAG has 7 nodes:
  1042. t0: ch = EntryToken
  1043. t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  1044. t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  1045.  
  1046.  
  1047. ===== Instruction selection begins: BB#1 ''
  1048. Selecting: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  1049.  
  1050. ISEL: Starting pattern match on root node: t7: ch = br t5, BasicBlock:ch< 0x3c68d18>
  1051.  
  1052. Initial Opcode index to 1281
  1053. Morphed node: t7: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t5
  1054.  
  1055. ISEL: Match complete!
  1056. Selecting: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  1057.  
  1058. ISEL: Starting pattern match on root node: t5: ch = store<ST4[%1]> t0, Constant:i32<1>, FrameIndex:i32<0>, undef:i32
  1059.  
  1060. Initial Opcode index to 336
  1061. Skipped scope entry (due to false predicate) at index 348, continuing at 418
  1062. Match failed at index 425
  1063. Continuing at 437
  1064. Morphed node: t5: ch = STRi32_r32<Mem:ST4[%1]> Constant:i32<1>, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1065.  
  1066. ISEL: Match complete!
  1067. Selecting: t6: ch = BasicBlock< 0x3c68d18>
  1068.  
  1069. Selecting: t1: i32 = Constant<1>
  1070.  
  1071. ISEL: Starting pattern match on root node: t1: i32 = Constant<1>
  1072.  
  1073. Initial Opcode index to 929
  1074. Morphed node: t1: i32 = MOVi16ri TargetConstant:i32<1>
  1075.  
  1076. ISEL: Match complete!
  1077. Selecting: t0: ch = EntryToken
  1078.  
  1079. ===== Instruction selection ends:
  1080. Selected selection DAG: BB#1 'main:'
  1081. SelectionDAG has 8 nodes:
  1082. t1: i32 = MOVi16ri TargetConstant:i32<1>
  1083. t0: ch = EntryToken
  1084. t5: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1085. t7: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t5
  1086.  
  1087.  
  1088. ********** List Scheduling BB#1 '' **********
  1089. SU(0): t7: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t5
  1090.  
  1091. # preds left : 1
  1092. # succs left : 0
  1093. # rdefs left : 0
  1094. Latency : 1
  1095. Depth : 2
  1096. Height : 0
  1097. Predecessors:
  1098. ch SU(1): Latency=1
  1099. SU(1): t5: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1100.  
  1101. # preds left : 1
  1102. # succs left : 1
  1103. # rdefs left : 0
  1104. Latency : 1
  1105. Depth : 1
  1106. Height : 1
  1107. Predecessors:
  1108. val SU(2): Latency=1
  1109. Successors:
  1110. ch SU(0): Latency=1
  1111. SU(2): t1: i32 = MOVi16ri TargetConstant:i32<1>
  1112.  
  1113. # preds left : 0
  1114. # succs left : 1
  1115. # rdefs left : 1
  1116. Latency : 1
  1117. Depth : 0
  1118. Height : 2
  1119. Successors:
  1120. val SU(1): Latency=1
  1121.  
  1122. Examining Available:
  1123. Height 0: SU(0): t7: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t5
  1124.  
  1125.  
  1126. *** Scheduling [0]: SU(0): t7: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t5
  1127.  
  1128.  
  1129. Examining Available:
  1130. Height 1: SU(1): t5: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1131.  
  1132.  
  1133. *** Scheduling [1]: SU(1): t5: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1134.  
  1135.  
  1136. Examining Available:
  1137. Height 2: SU(2): t1: i32 = MOVi16ri TargetConstant:i32<1>
  1138.  
  1139.  
  1140. *** Scheduling [2]: SU(2): t1: i32 = MOVi16ri TargetConstant:i32<1>
  1141.  
  1142. *** Final schedule ***
  1143. SU(2): t1: i32 = MOVi16ri TargetConstant:i32<1>
  1144.  
  1145. SU(1): t5: ch = STRi32_r32<Mem:ST4[%1]> t1, TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1146.  
  1147. SU(0): t7: ch = BNONE32 BasicBlock:ch< 0x3c68d18>, t5
  1148.  
  1149.  
  1150. Total amount of phi nodes to update: 0
  1151. Initial selection DAG: BB#3 'main:'
  1152. SelectionDAG has 8 nodes:
  1153. t0: ch = EntryToken
  1154. t2: i32 = Constant<0>
  1155. t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1156. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1157. t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1158.  
  1159.  
  1160.  
  1161. Combining: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1162.  
  1163. Combining: t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1164.  
  1165. Combining: t5: i32 = Register %R0
  1166.  
  1167. Combining: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1168.  
  1169. Combining: t3: i32 = undef
  1170.  
  1171. Combining: t1: i32 = FrameIndex<0>
  1172.  
  1173. Combining: t0: ch = EntryToken
  1174. Optimized lowered selection DAG: BB#3 'main:'
  1175. SelectionDAG has 7 nodes:
  1176. t0: ch = EntryToken
  1177. t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1178. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1179. t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1180.  
  1181.  
  1182. Legally typed node: t5: i32 = Register %R0
  1183.  
  1184. Legally typed node: t3: i32 = undef
  1185.  
  1186. Legally typed node: t1: i32 = FrameIndex<0>
  1187.  
  1188. Legally typed node: t0: ch = EntryToken
  1189.  
  1190. Legally typed node: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1191.  
  1192. Legally typed node: t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1193.  
  1194. Legally typed node: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1195.  
  1196. Legally typed node: t65535: ch = handlenode t7
  1197.  
  1198. Type-legalized selection DAG: BB#3 'main:'
  1199. SelectionDAG has 7 nodes:
  1200. t0: ch = EntryToken
  1201. t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1202. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1203. t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1204.  
  1205.  
  1206.  
  1207. Legalizing: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1208.  
  1209. Legalizing: t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1210.  
  1211. Legalizing: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1212.  
  1213. Legalizing: t5: i32 = Register %R0
  1214.  
  1215. Legalizing: t3: i32 = undef
  1216.  
  1217. Legalizing: t1: i32 = FrameIndex<0>
  1218.  
  1219. Legalizing: t0: ch = EntryToken
  1220. Legalized selection DAG: BB#3 'main:'
  1221. SelectionDAG has 7 nodes:
  1222. t0: ch = EntryToken
  1223. t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1224. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1225. t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1226.  
  1227.  
  1228.  
  1229. Legalizing: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1230.  
  1231. Combining: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1232.  
  1233. Legalizing: t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1234.  
  1235. Combining: t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1236.  
  1237. Legalizing: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1238.  
  1239. Combining: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1240.  
  1241. Legalizing: t5: i32 = Register %R0
  1242.  
  1243. Combining: t5: i32 = Register %R0
  1244.  
  1245. Legalizing: t3: i32 = undef
  1246.  
  1247. Combining: t3: i32 = undef
  1248.  
  1249. Legalizing: t1: i32 = FrameIndex<0>
  1250.  
  1251. Combining: t1: i32 = FrameIndex<0>
  1252.  
  1253. Legalizing: t0: ch = EntryToken
  1254.  
  1255. Combining: t0: ch = EntryToken
  1256. Optimized legalized selection DAG: BB#3 'main:'
  1257. SelectionDAG has 7 nodes:
  1258. t0: ch = EntryToken
  1259. t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1260. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1261. t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1262.  
  1263.  
  1264. ===== Instruction selection begins: BB#3 ''
  1265. Selecting: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1266.  
  1267. ISEL: Starting pattern match on root node: t7: ch = EpiphanyISD::RTS t6, Register:i32 %R0, t6:1
  1268.  
  1269. Initial Opcode index to 1246
  1270. Morphed node: t7: ch = RTS Register:i32 %R0, t6, t6:1
  1271.  
  1272. ISEL: Match complete!
  1273. Selecting: t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1274.  
  1275. Selecting: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1276.  
  1277. ISEL: Starting pattern match on root node: t4: i32,ch = load<LD4[%1]> t0, FrameIndex:i32<0>, undef:i32
  1278.  
  1279. Initial Opcode index to 124
  1280. Skipped scope entry (due to false predicate) at index 131, continuing at 167
  1281. Skipped scope entry (due to false predicate) at index 168, continuing at 204
  1282. Skipped scope entry (due to false predicate) at index 205, continuing at 241
  1283. Skipped scope entry (due to false predicate) at index 242, continuing at 278
  1284. TypeSwitch[i32] from 281 to 284
  1285. Match failed at index 288
  1286. Continuing at 300
  1287. Morphed node: t4: i32,ch = LDRi32_r32<Mem:LD4[%1]> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1288.  
  1289. ISEL: Match complete!
  1290. Selecting: t5: i32 = Register %R0
  1291.  
  1292. Selecting: t0: ch = EntryToken
  1293.  
  1294. ===== Instruction selection ends:
  1295. Selected selection DAG: BB#3 'main:'
  1296. SelectionDAG has 7 nodes:
  1297. t0: ch = EntryToken
  1298. t4: i32,ch = LDRi32_r32<Mem:LD4[%1]> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1299. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1300. t7: ch = RTS Register:i32 %R0, t6, t6:1
  1301.  
  1302.  
  1303. ********** List Scheduling BB#3 '' **********
  1304. SU(0): t7: ch = RTS Register:i32 %R0, t6, t6:1
  1305.  
  1306. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1307.  
  1308. # preds left : 1
  1309. # succs left : 0
  1310. # rdefs left : 0
  1311. Latency : 1
  1312. Depth : 1
  1313. Height : 0
  1314. Predecessors:
  1315. val SU(1): Latency=1
  1316. SU(1): t4: i32,ch = LDRi32_r32<Mem:LD4[%1]> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1317.  
  1318. # preds left : 0
  1319. # succs left : 1
  1320. # rdefs left : 1
  1321. Latency : 1
  1322. Depth : 0
  1323. Height : 1
  1324. Successors:
  1325. val SU(0): Latency=1
  1326.  
  1327. Examining Available:
  1328. Height 0: SU(0): t7: ch = RTS Register:i32 %R0, t6, t6:1
  1329.  
  1330. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1331.  
  1332.  
  1333. *** Scheduling [0]: SU(0): t7: ch = RTS Register:i32 %R0, t6, t6:1
  1334.  
  1335. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1336.  
  1337.  
  1338. Examining Available:
  1339. Height 1: SU(1): t4: i32,ch = LDRi32_r32<Mem:LD4[%1]> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1340.  
  1341.  
  1342. *** Scheduling [1]: SU(1): t4: i32,ch = LDRi32_r32<Mem:LD4[%1]> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1343.  
  1344. *** Final schedule ***
  1345. SU(1): t4: i32,ch = LDRi32_r32<Mem:LD4[%1]> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, t0
  1346.  
  1347. SU(0): t7: ch = RTS Register:i32 %R0, t6, t6:1
  1348.  
  1349. t6: ch,glue = CopyToReg t0, Register:i32 %R0, t4
  1350.  
  1351.  
  1352. Total amount of phi nodes to update: 0
  1353. *** MachineFunction at end of ISel ***
  1354. # Machine code for function main: Properties: <SSA, tracking liveness, HasVRegs>
  1355. Frame Objects:
  1356. fi#0: size=4, align=4, at location [SP]
  1357. fi#1: size=4, align=4, at location [SP]
  1358.  
  1359. BB#0: derived from LLVM BB %0
  1360. %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1361. STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1362. %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1363. STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1364. %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1365. %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1366. BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1367. BNONE32 <BB#1>, %STATUS<imp-use>
  1368. Successors according to CFG: BB#1 BB#2
  1369.  
  1370. BB#1: derived from LLVM BB %4
  1371. Predecessors according to CFG: BB#0
  1372. %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1373. STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1374. BNONE32 <BB#3>, %STATUS<imp-use>
  1375. Successors according to CFG: BB#3(?%)
  1376.  
  1377. BB#2: derived from LLVM BB %5
  1378. Predecessors according to CFG: BB#0
  1379. %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1380. STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1381. BNONE32 <BB#3>, %STATUS<imp-use>
  1382. Successors according to CFG: BB#3(?%)
  1383.  
  1384. BB#3: derived from LLVM BB %6
  1385. Predecessors according to CFG: BB#2 BB#1
  1386. %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1387. %R0<def> = COPY %vreg6; GPR32:%vreg6
  1388. RTS %R0<imp-use>
  1389.  
  1390. # End machine code for function main.
  1391.  
  1392. # *** IR Dump After Expand ISel Pseudo-instructions ***:
  1393. # Machine code for function main: Properties: <SSA, tracking liveness, HasVRegs>
  1394. Frame Objects:
  1395. fi#0: size=4, align=4, at location [SP]
  1396. fi#1: size=4, align=4, at location [SP]
  1397.  
  1398. BB#0: derived from LLVM BB %0
  1399. %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1400. STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1401. %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1402. STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1403. %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1404. %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1405. BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1406. BNONE32 <BB#1>, %STATUS<imp-use>
  1407. Successors according to CFG: BB#1 BB#2
  1408.  
  1409. BB#1: derived from LLVM BB %4
  1410. Predecessors according to CFG: BB#0
  1411. %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1412. STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1413. BNONE32 <BB#3>, %STATUS<imp-use>
  1414. Successors according to CFG: BB#3(?%)
  1415.  
  1416. BB#2: derived from LLVM BB %5
  1417. Predecessors according to CFG: BB#0
  1418. %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1419. STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1420. BNONE32 <BB#3>, %STATUS<imp-use>
  1421. Successors according to CFG: BB#3(?%)
  1422.  
  1423. BB#3: derived from LLVM BB %6
  1424. Predecessors according to CFG: BB#2 BB#1
  1425. %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1426. %R0<def> = COPY %vreg6; GPR32:%vreg6
  1427. RTS %R0<imp-use>
  1428.  
  1429. # End machine code for function main.
  1430.  
  1431. # *** IR Dump After Local Stack Slot Allocation ***:
  1432. # Machine code for function main: Properties: <SSA, tracking liveness, HasVRegs>
  1433. Frame Objects:
  1434. fi#0: size=4, align=4, at location [SP]
  1435. fi#1: size=4, align=4, at location [SP]
  1436.  
  1437. BB#0: derived from LLVM BB %0
  1438. %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1439. STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1440. %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1441. STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1442. %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1443. %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1444. BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1445. BNONE32 <BB#1>, %STATUS<imp-use>
  1446. Successors according to CFG: BB#1 BB#2
  1447.  
  1448. BB#1: derived from LLVM BB %4
  1449. Predecessors according to CFG: BB#0
  1450. %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1451. STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1452. BNONE32 <BB#3>, %STATUS<imp-use>
  1453. Successors according to CFG: BB#3(?%)
  1454.  
  1455. BB#2: derived from LLVM BB %5
  1456. Predecessors according to CFG: BB#0
  1457. %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1458. STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1459. BNONE32 <BB#3>, %STATUS<imp-use>
  1460. Successors according to CFG: BB#3(?%)
  1461.  
  1462. BB#3: derived from LLVM BB %6
  1463. Predecessors according to CFG: BB#2 BB#1
  1464. %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1465. %R0<def> = COPY %vreg6; GPR32:%vreg6
  1466. RTS %R0<imp-use>
  1467.  
  1468. # End machine code for function main.
  1469.  
  1470. # *** IR Dump After Eliminate PHI nodes for register allocation ***:
  1471. # Machine code for function main: Properties: <Post SSA, tracking liveness, HasVRegs>
  1472. Frame Objects:
  1473. fi#0: size=4, align=4, at location [SP]
  1474. fi#1: size=4, align=4, at location [SP]
  1475.  
  1476. BB#0: derived from LLVM BB %0
  1477. %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1478. STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1479. %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1480. STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1481. %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1482. %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1483. BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1484. BNONE32 <BB#1>, %STATUS<imp-use>
  1485. Successors according to CFG: BB#1 BB#2
  1486.  
  1487. BB#1: derived from LLVM BB %4
  1488. Predecessors according to CFG: BB#0
  1489. %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1490. STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1491. BNONE32 <BB#3>, %STATUS<imp-use>
  1492. Successors according to CFG: BB#3(?%)
  1493.  
  1494. BB#2: derived from LLVM BB %5
  1495. Predecessors according to CFG: BB#0
  1496. %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1497. STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1498. BNONE32 <BB#3>, %STATUS<imp-use>
  1499. Successors according to CFG: BB#3(?%)
  1500.  
  1501. BB#3: derived from LLVM BB %6
  1502. Predecessors according to CFG: BB#2 BB#1
  1503. %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1504. %R0<def> = COPY %vreg6; GPR32:%vreg6
  1505. RTS %R0<imp-use>
  1506.  
  1507. # End machine code for function main.
  1508.  
  1509. ********** REWRITING TWO-ADDR INSTRS **********
  1510. ********** Function: main
  1511. # *** IR Dump After Two-Address instruction pass ***:
  1512. # Machine code for function main: Properties: <Post SSA, tracking liveness, HasVRegs>
  1513. Frame Objects:
  1514. fi#0: size=4, align=4, at location [SP]
  1515. fi#1: size=4, align=4, at location [SP]
  1516.  
  1517. BB#0: derived from LLVM BB %0
  1518. %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1519. STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1520. %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1521. STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1522. %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1523. %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1524. BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1525. BNONE32 <BB#1>, %STATUS<imp-use>
  1526. Successors according to CFG: BB#1 BB#2
  1527.  
  1528. BB#1: derived from LLVM BB %4
  1529. Predecessors according to CFG: BB#0
  1530. %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1531. STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1532. BNONE32 <BB#3>, %STATUS<imp-use>
  1533. Successors according to CFG: BB#3(?%)
  1534.  
  1535. BB#2: derived from LLVM BB %5
  1536. Predecessors according to CFG: BB#0
  1537. %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1538. STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1539. BNONE32 <BB#3>, %STATUS<imp-use>
  1540. Successors according to CFG: BB#3(?%)
  1541.  
  1542. BB#3: derived from LLVM BB %6
  1543. Predecessors according to CFG: BB#2 BB#1
  1544. %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1545. %R0<def> = COPY %vreg6; GPR32:%vreg6
  1546. RTS %R0<imp-use>
  1547.  
  1548. # End machine code for function main.
  1549.  
  1550. ********** FAST REGISTER ALLOCATION **********
  1551. ********** Function: main
  1552.  
  1553. Allocating BB#0: derived from LLVM BB %0
  1554. %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1555. STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1556. %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1557. STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1558. %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1559. %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1560. BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1561. BNONE32 <BB#1>, %STATUS<imp-use>
  1562. Successors according to CFG: BB#1 BB#2
  1563.  
  1564. >> %vreg0<def> = MOVi16ri 0; GPR16:%vreg0
  1565. Regs:
  1566. AllocationOrder(GPR16) = [ %R0 %R1 %R2 %R3 %R4 %R5 %R6 %R7 ]
  1567. Allocating %vreg0 from GPR16
  1568. %R0 is disabled.
  1569. Register: %R0
  1570. Cost: 0
  1571. BestCost: 4294967295
  1572. Assigning %vreg0 to %R0
  1573. << %R0<def> = MOVi16ri 0
  1574.  
  1575. >> STRi32_r32 %vreg0<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg0
  1576. Regs: R0=%vreg0*
  1577. Killing last use: %vreg0<kill>
  1578. << STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1579.  
  1580. >> %vreg1<def> = MOVi16ri 1; GPR16:%vreg1
  1581. Regs: R0
  1582. Assigning %vreg1 to %R0
  1583. << %R0<def> = MOVi16ri 1
  1584.  
  1585. >> STRi32_r32 %vreg1, <fi#1>, 0; mem:ST4[%a] GPR16:%vreg1
  1586. Regs: R0=%vreg1*
  1587. << STRi32_r32 %R0, <fi#1>, 0; mem:ST4[%a]
  1588.  
  1589. >> %vreg2<def> = MOVi16ri 4; GPR16:%vreg2
  1590. Regs: R0=%vreg1*
  1591. Allocating %vreg2 from GPR16
  1592. Register: %R0
  1593. Cost: 100
  1594. BestCost: 4294967295
  1595. %R1 is disabled.
  1596. Register: %R1
  1597. Cost: 0
  1598. BestCost: 100
  1599. Assigning %vreg2 to %R1
  1600. << %R1<def> = MOVi16ri 4
  1601.  
  1602. >> %vreg3<def> = SUBrr_r32 %vreg1, %vreg2<kill>, %STATUS<imp-def,dead>; GPR32:%vreg3 GPR16:%vreg1,%vreg2
  1603. Regs: R0=%vreg1* R1=%vreg2*
  1604. Killing last use: %vreg1
  1605. Killing last use: %vreg2<kill>
  1606. AllocationOrder(GPR32) = [ %R0 %R1 %R2 %R3 %R12 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R44 %R45 %R46 %R47 %R48 %R49 %R50 %R51 %R52 %R53 %R54 %R55 %R56 %R57 %R58 %R59 %R60 %R61 %R62 %R63 %R4 %R5 %R6 %R7 %R8 %R15 %R32 %R33 %R34 %R35 %R36 %R37 %R38 %R39 %R40 %R41 %R42 %R43 ]
  1607. Assigning %vreg3 to %R0
  1608. << %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1609.  
  1610. >> BLT32 %vreg3<kill>, <BB#2>, %STATUS<imp-use>; GPR32:%vreg3
  1611. Regs: R0=%vreg3* R1
  1612. Killing last use: %vreg3<kill>
  1613. << BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1614.  
  1615. >> BNONE32 <BB#1>, %STATUS<imp-use>
  1616. Regs: R0 R1
  1617. << BNONE32 <BB#1>, %STATUS<imp-use>
  1618. Spilling live registers at end of block.
  1619. BB#0: derived from LLVM BB %0
  1620. %R0<def> = MOVi16ri 0
  1621. STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1622. %R0<def> = MOVi16ri 1
  1623. STRi32_r32 %R0, <fi#1>, 0; mem:ST4[%a]
  1624. %R1<def> = MOVi16ri 4
  1625. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1626. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1627. BNONE32 <BB#1>, %STATUS<imp-use>
  1628. Successors according to CFG: BB#1 BB#2
  1629.  
  1630. Allocating BB#1: derived from LLVM BB %4
  1631. Predecessors according to CFG: BB#0
  1632. %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1633. STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1634. BNONE32 <BB#3>, %STATUS<imp-use>
  1635. Successors according to CFG: BB#3(?%)
  1636.  
  1637. >> %vreg5<def> = MOVi16ri 1; GPR16:%vreg5
  1638. Regs:
  1639. Allocating %vreg5 from GPR16
  1640. %R0 is disabled.
  1641. Register: %R0
  1642. Cost: 0
  1643. BestCost: 4294967295
  1644. Assigning %vreg5 to %R0
  1645. << %R0<def> = MOVi16ri 1
  1646.  
  1647. >> STRi32_r32 %vreg5<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg5
  1648. Regs: R0=%vreg5*
  1649. Killing last use: %vreg5<kill>
  1650. << STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1651.  
  1652. >> BNONE32 <BB#3>, %STATUS<imp-use>
  1653. Regs: R0
  1654. << BNONE32 <BB#3>, %STATUS<imp-use>
  1655. Spilling live registers at end of block.
  1656. BB#1: derived from LLVM BB %4
  1657. Predecessors according to CFG: BB#0
  1658. %R0<def> = MOVi16ri 1
  1659. STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1660. BNONE32 <BB#3>, %STATUS<imp-use>
  1661. Successors according to CFG: BB#3(?%)
  1662.  
  1663. Allocating BB#2: derived from LLVM BB %5
  1664. Predecessors according to CFG: BB#0
  1665. %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1666. STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1667. BNONE32 <BB#3>, %STATUS<imp-use>
  1668. Successors according to CFG: BB#3(?%)
  1669.  
  1670. >> %vreg4<def> = MOVi16ri 0; GPR16:%vreg4
  1671. Regs:
  1672. Allocating %vreg4 from GPR16
  1673. %R0 is disabled.
  1674. Register: %R0
  1675. Cost: 0
  1676. BestCost: 4294967295
  1677. Assigning %vreg4 to %R0
  1678. << %R0<def> = MOVi16ri 0
  1679.  
  1680. >> STRi32_r32 %vreg4<kill>, <fi#0>, 0; mem:ST4[%1] GPR16:%vreg4
  1681. Regs: R0=%vreg4*
  1682. Killing last use: %vreg4<kill>
  1683. << STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1684.  
  1685. >> BNONE32 <BB#3>, %STATUS<imp-use>
  1686. Regs: R0
  1687. << BNONE32 <BB#3>, %STATUS<imp-use>
  1688. Spilling live registers at end of block.
  1689. BB#2: derived from LLVM BB %5
  1690. Predecessors according to CFG: BB#0
  1691. %R0<def> = MOVi16ri 0
  1692. STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1693. BNONE32 <BB#3>, %STATUS<imp-use>
  1694. Successors according to CFG: BB#3(?%)
  1695.  
  1696. Allocating BB#3: derived from LLVM BB %6
  1697. Predecessors according to CFG: BB#2 BB#1
  1698. %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1699. %R0<def> = COPY %vreg6; GPR32:%vreg6
  1700. RTS %R0<imp-use>
  1701.  
  1702. >> %vreg6<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1] GPR32:%vreg6
  1703. Regs:
  1704. %R0 is disabled.
  1705. Assigning %vreg6 to %R0
  1706. << %R0<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1]
  1707.  
  1708. >> %R0<def> = COPY %vreg6; GPR32:%vreg6
  1709. Regs: R0=%vreg6*
  1710. Killing last use: %vreg6
  1711. -- coalescing: %R0<def> = COPY %R0<kill>
  1712.  
  1713. >> RTS %R0<imp-use>
  1714. Regs: R0*
  1715. << RTS %R0<imp-use,kill>
  1716. Spilling live registers at end of block.
  1717. BB#3: derived from LLVM BB %6
  1718. Predecessors according to CFG: BB#2 BB#1
  1719. %R0<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1]
  1720. RTS %R0<imp-use,kill>
  1721. alloc FI(0) at SP[-4]
  1722. alloc FI(1) at SP[-8]
  1723.  
  1724. Function : main
  1725. <--------->
  1726. STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1727. FrameIndex : 0
  1728. spOffset : -4
  1729. stackSize : 8
  1730. Offset : 4
  1731. <--------->
  1732.  
  1733. Function : main
  1734. <--------->
  1735. STRi32_r32 %R0, <fi#1>, 0; mem:ST4[%a]
  1736. FrameIndex : 1
  1737. spOffset : -8
  1738. stackSize : 8
  1739. Offset : 0
  1740. <--------->
  1741.  
  1742. Function : main
  1743. <--------->
  1744. STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1745. FrameIndex : 0
  1746. spOffset : -4
  1747. stackSize : 8
  1748. Offset : 4
  1749. <--------->
  1750.  
  1751. Function : main
  1752. <--------->
  1753. %R0<def> = LDRi32_r32 <fi#0>, 0; mem:LD4[%1]
  1754. FrameIndex : 0
  1755. spOffset : -4
  1756. stackSize : 8
  1757. Offset : 4
  1758. <--------->
  1759.  
  1760. Function : main
  1761. <--------->
  1762. STRi32_r32 %R0<kill>, <fi#0>, 0; mem:ST4[%1]
  1763. FrameIndex : 0
  1764. spOffset : -4
  1765. stackSize : 8
  1766. Offset : 4
  1767. <--------->
  1768. # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization ***:
  1769. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  1770. Frame Objects:
  1771. fi#0: size=4, align=4, at location [SP-4]
  1772. fi#1: size=4, align=4, at location [SP-8]
  1773.  
  1774. BB#0: derived from LLVM BB %0
  1775. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  1776. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  1777. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  1778. CFI_INSTRUCTION <call frame instruction>
  1779. CFI_INSTRUCTION <call frame instruction>
  1780. %R0<def> = MOVi16ri 0
  1781. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1782. %R0<def> = MOVi16ri 1
  1783. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  1784. %R1<def> = MOVi16ri 4
  1785. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1786. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1787. BNONE32 <BB#1>, %STATUS<imp-use>
  1788. Successors according to CFG: BB#1 BB#2
  1789.  
  1790. BB#1: derived from LLVM BB %4
  1791. Predecessors according to CFG: BB#0
  1792. %R0<def> = MOVi16ri 1
  1793. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1794. BNONE32 <BB#3>, %STATUS<imp-use>
  1795. Successors according to CFG: BB#3(?%)
  1796.  
  1797. BB#2: derived from LLVM BB %5
  1798. Predecessors according to CFG: BB#0
  1799. %R0<def> = MOVi16ri 0
  1800. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1801. BNONE32 <BB#3>, %STATUS<imp-use>
  1802. Successors according to CFG: BB#3(?%)
  1803.  
  1804. BB#3: derived from LLVM BB %6
  1805. Predecessors according to CFG: BB#2 BB#1
  1806. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  1807. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  1808. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  1809. RTS %R0<imp-use,kill>
  1810.  
  1811. # End machine code for function main.
  1812.  
  1813. Machine Function
  1814. ********** EXPANDING POST-RA PSEUDO INSTRS **********
  1815. ********** Function: main
  1816. # *** IR Dump After Post-RA pseudo instruction expansion pass ***:
  1817. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  1818. Frame Objects:
  1819. fi#0: size=4, align=4, at location [SP-4]
  1820. fi#1: size=4, align=4, at location [SP-8]
  1821.  
  1822. BB#0: derived from LLVM BB %0
  1823. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  1824. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  1825. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  1826. CFI_INSTRUCTION <call frame instruction>
  1827. CFI_INSTRUCTION <call frame instruction>
  1828. %R0<def> = MOVi16ri 0
  1829. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1830. %R0<def> = MOVi16ri 1
  1831. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  1832. %R1<def> = MOVi16ri 4
  1833. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1834. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1835. BNONE32 <BB#1>, %STATUS<imp-use>
  1836. Successors according to CFG: BB#1 BB#2
  1837.  
  1838. BB#1: derived from LLVM BB %4
  1839. Predecessors according to CFG: BB#0
  1840. %R0<def> = MOVi16ri 1
  1841. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1842. BNONE32 <BB#3>, %STATUS<imp-use>
  1843. Successors according to CFG: BB#3(?%)
  1844.  
  1845. BB#2: derived from LLVM BB %5
  1846. Predecessors according to CFG: BB#0
  1847. %R0<def> = MOVi16ri 0
  1848. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1849. BNONE32 <BB#3>, %STATUS<imp-use>
  1850. Successors according to CFG: BB#3(?%)
  1851.  
  1852. BB#3: derived from LLVM BB %6
  1853. Predecessors according to CFG: BB#2 BB#1
  1854. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  1855. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  1856. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  1857. JR32 %LR
  1858.  
  1859. # End machine code for function main.
  1860.  
  1861. # *** IR Dump After Analyze Machine Code For Garbage Collection ***:
  1862. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  1863. Frame Objects:
  1864. fi#0: size=4, align=4, at location [SP-4]
  1865. fi#1: size=4, align=4, at location [SP-8]
  1866.  
  1867. BB#0: derived from LLVM BB %0
  1868. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  1869. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  1870. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  1871. CFI_INSTRUCTION <call frame instruction>
  1872. CFI_INSTRUCTION <call frame instruction>
  1873. %R0<def> = MOVi16ri 0
  1874. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1875. %R0<def> = MOVi16ri 1
  1876. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  1877. %R1<def> = MOVi16ri 4
  1878. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1879. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1880. BNONE32 <BB#1>, %STATUS<imp-use>
  1881. Successors according to CFG: BB#1 BB#2
  1882.  
  1883. BB#1: derived from LLVM BB %4
  1884. Predecessors according to CFG: BB#0
  1885. %R0<def> = MOVi16ri 1
  1886. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1887. BNONE32 <BB#3>, %STATUS<imp-use>
  1888. Successors according to CFG: BB#3(?%)
  1889.  
  1890. BB#2: derived from LLVM BB %5
  1891. Predecessors according to CFG: BB#0
  1892. %R0<def> = MOVi16ri 0
  1893. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1894. BNONE32 <BB#3>, %STATUS<imp-use>
  1895. Successors according to CFG: BB#3(?%)
  1896.  
  1897. BB#3: derived from LLVM BB %6
  1898. Predecessors according to CFG: BB#2 BB#1
  1899. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  1900. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  1901. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  1902. JR32 %LR
  1903.  
  1904. # End machine code for function main.
  1905.  
  1906. # *** IR Dump After Contiguously Lay Out Funclets ***:
  1907. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  1908. Frame Objects:
  1909. fi#0: size=4, align=4, at location [SP-4]
  1910. fi#1: size=4, align=4, at location [SP-8]
  1911.  
  1912. BB#0: derived from LLVM BB %0
  1913. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  1914. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  1915. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  1916. CFI_INSTRUCTION <call frame instruction>
  1917. CFI_INSTRUCTION <call frame instruction>
  1918. %R0<def> = MOVi16ri 0
  1919. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1920. %R0<def> = MOVi16ri 1
  1921. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  1922. %R1<def> = MOVi16ri 4
  1923. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1924. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1925. BNONE32 <BB#1>, %STATUS<imp-use>
  1926. Successors according to CFG: BB#1 BB#2
  1927.  
  1928. BB#1: derived from LLVM BB %4
  1929. Predecessors according to CFG: BB#0
  1930. %R0<def> = MOVi16ri 1
  1931. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1932. BNONE32 <BB#3>, %STATUS<imp-use>
  1933. Successors according to CFG: BB#3(?%)
  1934.  
  1935. BB#2: derived from LLVM BB %5
  1936. Predecessors according to CFG: BB#0
  1937. %R0<def> = MOVi16ri 0
  1938. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1939. BNONE32 <BB#3>, %STATUS<imp-use>
  1940. Successors according to CFG: BB#3(?%)
  1941.  
  1942. BB#3: derived from LLVM BB %6
  1943. Predecessors according to CFG: BB#2 BB#1
  1944. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  1945. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  1946. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  1947. JR32 %LR
  1948.  
  1949. # End machine code for function main.
  1950.  
  1951. ********** COMPUTING STACKMAP LIVENESS: main **********
  1952. # *** IR Dump After StackMap Liveness Analysis ***:
  1953. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  1954. Frame Objects:
  1955. fi#0: size=4, align=4, at location [SP-4]
  1956. fi#1: size=4, align=4, at location [SP-8]
  1957.  
  1958. BB#0: derived from LLVM BB %0
  1959. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  1960. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  1961. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  1962. CFI_INSTRUCTION <call frame instruction>
  1963. CFI_INSTRUCTION <call frame instruction>
  1964. %R0<def> = MOVi16ri 0
  1965. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1966. %R0<def> = MOVi16ri 1
  1967. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  1968. %R1<def> = MOVi16ri 4
  1969. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  1970. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  1971. BNONE32 <BB#1>, %STATUS<imp-use>
  1972. Successors according to CFG: BB#1 BB#2
  1973.  
  1974. BB#1: derived from LLVM BB %4
  1975. Predecessors according to CFG: BB#0
  1976. %R0<def> = MOVi16ri 1
  1977. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1978. BNONE32 <BB#3>, %STATUS<imp-use>
  1979. Successors according to CFG: BB#3(?%)
  1980.  
  1981. BB#2: derived from LLVM BB %5
  1982. Predecessors according to CFG: BB#0
  1983. %R0<def> = MOVi16ri 0
  1984. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  1985. BNONE32 <BB#3>, %STATUS<imp-use>
  1986. Successors according to CFG: BB#3(?%)
  1987.  
  1988. BB#3: derived from LLVM BB %6
  1989. Predecessors according to CFG: BB#2 BB#1
  1990. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  1991. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  1992. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  1993. JR32 %LR
  1994.  
  1995. # End machine code for function main.
  1996.  
  1997.  
  1998. Debug Range Extension
  1999. MBB: :
  2000. MBB: :
  2001. MBB: :
  2002. MBB: :
  2003.  
  2004. join MBB:
  2005. join MBB:
  2006. join MBB:
  2007. join MBB:
  2008. MBB: :
  2009. MBB: :
  2010. MBB: :
  2011. MBB: :
  2012.  
  2013. MBB: :
  2014. MBB: :
  2015. MBB: :
  2016. MBB: :
  2017.  
  2018. # *** IR Dump After Live DEBUG_VALUE analysis ***:
  2019. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  2020. Frame Objects:
  2021. fi#0: size=4, align=4, at location [SP-4]
  2022. fi#1: size=4, align=4, at location [SP-8]
  2023.  
  2024. BB#0: derived from LLVM BB %0
  2025. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  2026. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  2027. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  2028. CFI_INSTRUCTION <call frame instruction>
  2029. CFI_INSTRUCTION <call frame instruction>
  2030. %R0<def> = MOVi16ri 0
  2031. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2032. %R0<def> = MOVi16ri 1
  2033. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  2034. %R1<def> = MOVi16ri 4
  2035. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  2036. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  2037. BNONE32 <BB#1>, %STATUS<imp-use>
  2038. Successors according to CFG: BB#1 BB#2
  2039.  
  2040. BB#1: derived from LLVM BB %4
  2041. Predecessors according to CFG: BB#0
  2042. %R0<def> = MOVi16ri 1
  2043. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2044. BNONE32 <BB#3>, %STATUS<imp-use>
  2045. Successors according to CFG: BB#3(?%)
  2046.  
  2047. BB#2: derived from LLVM BB %5
  2048. Predecessors according to CFG: BB#0
  2049. %R0<def> = MOVi16ri 0
  2050. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2051. BNONE32 <BB#3>, %STATUS<imp-use>
  2052. Successors according to CFG: BB#3(?%)
  2053.  
  2054. BB#3: derived from LLVM BB %6
  2055. Predecessors according to CFG: BB#2 BB#1
  2056. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  2057. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  2058. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  2059. JR32 %LR
  2060.  
  2061. # End machine code for function main.
  2062.  
  2063. # *** IR Dump After Insert XRay ops ***:
  2064. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  2065. Frame Objects:
  2066. fi#0: size=4, align=4, at location [SP-4]
  2067. fi#1: size=4, align=4, at location [SP-8]
  2068.  
  2069. BB#0: derived from LLVM BB %0
  2070. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  2071. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  2072. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  2073. CFI_INSTRUCTION <call frame instruction>
  2074. CFI_INSTRUCTION <call frame instruction>
  2075. %R0<def> = MOVi16ri 0
  2076. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2077. %R0<def> = MOVi16ri 1
  2078. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  2079. %R1<def> = MOVi16ri 4
  2080. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  2081. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  2082. BNONE32 <BB#1>, %STATUS<imp-use>
  2083. Successors according to CFG: BB#1 BB#2
  2084.  
  2085. BB#1: derived from LLVM BB %4
  2086. Predecessors according to CFG: BB#0
  2087. %R0<def> = MOVi16ri 1
  2088. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2089. BNONE32 <BB#3>, %STATUS<imp-use>
  2090. Successors according to CFG: BB#3(?%)
  2091.  
  2092. BB#2: derived from LLVM BB %5
  2093. Predecessors according to CFG: BB#0
  2094. %R0<def> = MOVi16ri 0
  2095. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2096. BNONE32 <BB#3>, %STATUS<imp-use>
  2097. Successors according to CFG: BB#3(?%)
  2098.  
  2099. BB#3: derived from LLVM BB %6
  2100. Predecessors according to CFG: BB#2 BB#1
  2101. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  2102. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  2103. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  2104. JR32 %LR
  2105.  
  2106. # End machine code for function main.
  2107.  
  2108. # *** IR Dump After Implement the 'patchable-function' attribute ***:
  2109. # Machine code for function main: Properties: <Post SSA, tracking liveness, AllVRegsAllocated>
  2110. Frame Objects:
  2111. fi#0: size=4, align=4, at location [SP-4]
  2112. fi#1: size=4, align=4, at location [SP-8]
  2113.  
  2114. BB#0: derived from LLVM BB %0
  2115. %FP<def> = STRi32_r32 %SP, 0; flags: FrameSetup
  2116. %SP<def> = ADD32ri %SP, -8, %STATUS<imp-def>
  2117. %FP<def> = MOVi32rr %SP; flags: FrameSetup
  2118. CFI_INSTRUCTION <call frame instruction>
  2119. CFI_INSTRUCTION <call frame instruction>
  2120. %R0<def> = MOVi16ri 0
  2121. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2122. %R0<def> = MOVi16ri 1
  2123. STRi32_r32 %R0, %FP, 0; mem:ST4[%a]
  2124. %R1<def> = MOVi16ri 4
  2125. %R0<def> = SUBrr_r32 %R0<kill>, %R1<kill>, %STATUS<imp-def,dead>
  2126. BLT32 %R0<kill>, <BB#2>, %STATUS<imp-use>
  2127. BNONE32 <BB#1>, %STATUS<imp-use>
  2128. Successors according to CFG: BB#1 BB#2
  2129.  
  2130. BB#1: derived from LLVM BB %4
  2131. Predecessors according to CFG: BB#0
  2132. %R0<def> = MOVi16ri 1
  2133. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2134. BNONE32 <BB#3>, %STATUS<imp-use>
  2135. Successors according to CFG: BB#3(?%)
  2136.  
  2137. BB#2: derived from LLVM BB %5
  2138. Predecessors according to CFG: BB#0
  2139. %R0<def> = MOVi16ri 0
  2140. STRi32_r32 %R0<kill>, %FP, 4; mem:ST4[%1]
  2141. BNONE32 <BB#3>, %STATUS<imp-use>
  2142. Successors according to CFG: BB#3(?%)
  2143.  
  2144. BB#3: derived from LLVM BB %6
  2145. Predecessors according to CFG: BB#2 BB#1
  2146. %R0<def> = LDRi32_r32 %FP, 4; mem:LD4[%1]
  2147. %FP<def> = LDRi32_r32 %SP, 8; flags: FrameSetup
  2148. %SP<def> = ADD32ri %SP, 8, %STATUS<imp-def>
  2149. JR32 %LR
  2150.  
  2151. # End machine code for function main.
  2152.  
  2153. assembler backend - pre-layout
  2154. --
  2155. <MCAssembler
  2156. Sections:[
  2157. <MCSection Fragments:[
  2158. <MCAlignFragment<MCFragment 0x3c5fa80 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0> (emit nops)
  2159. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2160. <MCAlignFragment<MCFragment 0x3c746c0 LayoutOrder:4294967295 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0> (emit nops)
  2161. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2162. <MCDataFragment<MCFragment 0x3c74900 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:1 BundlePadding:0>
  2163. Contents:[5C,F4,00,24,1B,B4,FF,24,EF,F4,02,24,03,00,DC,1C,00,04,23,00,5C,1C,00,04,83,20,BF,00,0A,00,88,00,00,00,E8,00,00,00,23,00,DC,1C,00,04,E8,00,00,00,03,00,DC,1C,00,04,E8,00,00,00,CC,1C,00,04,4C,F5,00,24,1B,B4,01,24,4F,19,02,04] (74 bytes),
  2164. Fixups:[<MCFixup Offset:30 Value:.LBB0_2 Kind:136>,
  2165. <MCFixup Offset:34 Value:.LBB0_1 Kind:136>,
  2166. <MCFixup Offset:44 Value:.LBB0_3 Kind:136>,
  2167. <MCFixup Offset:54 Value:.LBB0_3 Kind:136>]>]>,
  2168. <MCSection Fragments:[
  2169. <MCDataFragment<MCFragment 0x3c74c10 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2170. Contents:[00,63,6C,61,6E,67,20,76,65,72,73,69,6F,6E,20,33,2E,38,2E,30,2D,32,75,62,75,6E,74,75,34,20,28,74,61,67,73,2F,52,45,4C,45,41,53,45,5F,33,38,30,2F,66,69,6E,61,6C,29,00] (55 bytes)>]>,
  2171. <MCSection Fragments:[
  2172. <MCDataFragment<MCFragment 0x3c74dc0 LayoutOrder:4294967295 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2173. Contents:[] (0 bytes)>]>,
  2174. <MCSection Fragments:[
  2175. <MCDataFragment<MCFragment 0x3c74ef0 LayoutOrder:4294967295 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2176. Contents:[00,00,00,00,00,00,00,00,01,7A,52,00,01,7C,65,01,1B,0C,0D,00] (20 bytes),
  2177. Fixups:[<MCFixup Offset:0 Value:(-)-4 Kind:2>]>,
  2178. <MCAlignFragment<MCFragment 0x3c74fe0 LayoutOrder:4294967295 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2179. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2180. <MCDataFragment<MCFragment 0x3c75030 LayoutOrder:4294967295 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2181. Contents:[00,00,00,00,00,00,00,00,00,00,00,00,4A,00,00,00,00,4C,0D,0F,0E,08] (22 bytes),
  2182. Fixups:[<MCFixup Offset:0 Value:(-)-0 Kind:2>,
  2183. <MCFixup Offset:4 Value:(-)-0 Kind:2>,
  2184. <MCFixup Offset:8 Value:- Kind:2>]>,
  2185. <MCAlignFragment<MCFragment 0x3c6ebd0 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2186. Alignment:8 Value:0 ValueSize:1 MaxBytesToEmit:8>>,
  2187. <MCDataFragment<MCFragment 0x3c75160 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2188. Contents:[] (0 bytes)>]>],
  2189. Symbols:[(.text, Index:0, ),
  2190. (main, Index:0, ),
  2191. (, Index:0, ),
  2192. (, Index:0, ),
  2193. (, Index:0, ),
  2194. (.LBB0_2, Index:0, ),
  2195. (.LBB0_1, Index:0, ),
  2196. (.LBB0_3, Index:0, ),
  2197. (, Index:0, ),
  2198. (, Index:0, ),
  2199. (.comment, Index:0, ),
  2200. (.note.GNU-stack, Index:0, ),
  2201. (.eh_frame, Index:0, ),
  2202. (, Index:0, ),
  2203. (, Index:0, ),
  2204. (, Index:0, ),
  2205. (, Index:0, ),
  2206. (, Index:0, ),
  2207. (, Index:0, )]>
  2208. assembler backend - post-relaxation
  2209. --
  2210. <MCAssembler
  2211. Sections:[
  2212. <MCSection Fragments:[
  2213. <MCAlignFragment<MCFragment 0x3c5fa80 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0> (emit nops)
  2214. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2215. <MCAlignFragment<MCFragment 0x3c746c0 LayoutOrder:1 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0> (emit nops)
  2216. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2217. <MCDataFragment<MCFragment 0x3c74900 LayoutOrder:2 Offset:18446744073709551615 HasInstructions:1 BundlePadding:0>
  2218. Contents:[5C,F4,00,24,1B,B4,FF,24,EF,F4,02,24,03,00,DC,1C,00,04,23,00,5C,1C,00,04,83,20,BF,00,0A,00,88,00,00,00,E8,00,00,00,23,00,DC,1C,00,04,E8,00,00,00,03,00,DC,1C,00,04,E8,00,00,00,CC,1C,00,04,4C,F5,00,24,1B,B4,01,24,4F,19,02,04] (74 bytes),
  2219. Fixups:[<MCFixup Offset:30 Value:.LBB0_2 Kind:136>,
  2220. <MCFixup Offset:34 Value:.LBB0_1 Kind:136>,
  2221. <MCFixup Offset:44 Value:.LBB0_3 Kind:136>,
  2222. <MCFixup Offset:54 Value:.LBB0_3 Kind:136>]>]>,
  2223. <MCSection Fragments:[
  2224. <MCDataFragment<MCFragment 0x3c74c10 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2225. Contents:[00,63,6C,61,6E,67,20,76,65,72,73,69,6F,6E,20,33,2E,38,2E,30,2D,32,75,62,75,6E,74,75,34,20,28,74,61,67,73,2F,52,45,4C,45,41,53,45,5F,33,38,30,2F,66,69,6E,61,6C,29,00] (55 bytes)>]>,
  2226. <MCSection Fragments:[
  2227. <MCDataFragment<MCFragment 0x3c74dc0 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2228. Contents:[] (0 bytes)>]>,
  2229. <MCSection Fragments:[
  2230. <MCDataFragment<MCFragment 0x3c74ef0 LayoutOrder:0 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2231. Contents:[00,00,00,00,00,00,00,00,01,7A,52,00,01,7C,65,01,1B,0C,0D,00] (20 bytes),
  2232. Fixups:[<MCFixup Offset:0 Value:(-)-4 Kind:2>]>,
  2233. <MCAlignFragment<MCFragment 0x3c74fe0 LayoutOrder:1 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2234. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2235. <MCDataFragment<MCFragment 0x3c75030 LayoutOrder:2 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2236. Contents:[00,00,00,00,00,00,00,00,00,00,00,00,4A,00,00,00,00,4C,0D,0F,0E,08] (22 bytes),
  2237. Fixups:[<MCFixup Offset:0 Value:(-)-0 Kind:2>,
  2238. <MCFixup Offset:4 Value:(-)-0 Kind:2>,
  2239. <MCFixup Offset:8 Value:- Kind:2>]>,
  2240. <MCAlignFragment<MCFragment 0x3c6ebd0 LayoutOrder:3 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2241. Alignment:8 Value:0 ValueSize:1 MaxBytesToEmit:8>>,
  2242. <MCDataFragment<MCFragment 0x3c75160 LayoutOrder:4 Offset:18446744073709551615 HasInstructions:0 BundlePadding:0>
  2243. Contents:[] (0 bytes)>]>],
  2244. Symbols:[(.text, Index:0, ),
  2245. (main, Index:0, ),
  2246. (, Index:0, ),
  2247. (, Index:0, ),
  2248. (, Index:0, ),
  2249. (.LBB0_2, Index:0, ),
  2250. (.LBB0_1, Index:0, ),
  2251. (.LBB0_3, Index:0, ),
  2252. (, Index:0, ),
  2253. (, Index:0, ),
  2254. (.comment, Index:0, ),
  2255. (.note.GNU-stack, Index:0, ),
  2256. (.eh_frame, Index:0, ),
  2257. (, Index:0, ),
  2258. (, Index:0, ),
  2259. (, Index:0, ),
  2260. (, Index:0, ),
  2261. (, Index:0, ),
  2262. (, Index:0, )]>
  2263. assembler backend - final-layout
  2264. --
  2265. <MCAssembler
  2266. Sections:[
  2267. <MCSection Fragments:[
  2268. <MCAlignFragment<MCFragment 0x3c5fa80 LayoutOrder:0 Offset:0 HasInstructions:0 BundlePadding:0> (emit nops)
  2269. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2270. <MCAlignFragment<MCFragment 0x3c746c0 LayoutOrder:1 Offset:0 HasInstructions:0 BundlePadding:0> (emit nops)
  2271. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2272. <MCDataFragment<MCFragment 0x3c74900 LayoutOrder:2 Offset:0 HasInstructions:1 BundlePadding:0>
  2273. Contents:[5C,F4,00,24,1B,B4,FF,24,EF,F4,02,24,03,00,DC,1C,00,04,23,00,5C,1C,00,04,83,20,BF,00,0A,00,88,00,00,00,E8,00,00,00,23,00,DC,1C,00,04,E8,00,00,00,03,00,DC,1C,00,04,E8,00,00,00,CC,1C,00,04,4C,F5,00,24,1B,B4,01,24,4F,19,02,04] (74 bytes),
  2274. Fixups:[<MCFixup Offset:30 Value:.LBB0_2 Kind:136>,
  2275. <MCFixup Offset:34 Value:.LBB0_1 Kind:136>,
  2276. <MCFixup Offset:44 Value:.LBB0_3 Kind:136>,
  2277. <MCFixup Offset:54 Value:.LBB0_3 Kind:136>]>]>,
  2278. <MCSection Fragments:[
  2279. <MCDataFragment<MCFragment 0x3c74c10 LayoutOrder:0 Offset:0 HasInstructions:0 BundlePadding:0>
  2280. Contents:[00,63,6C,61,6E,67,20,76,65,72,73,69,6F,6E,20,33,2E,38,2E,30,2D,32,75,62,75,6E,74,75,34,20,28,74,61,67,73,2F,52,45,4C,45,41,53,45,5F,33,38,30,2F,66,69,6E,61,6C,29,00] (55 bytes)>]>,
  2281. <MCSection Fragments:[
  2282. <MCDataFragment<MCFragment 0x3c74dc0 LayoutOrder:0 Offset:0 HasInstructions:0 BundlePadding:0>
  2283. Contents:[] (0 bytes)>]>,
  2284. <MCSection Fragments:[
  2285. <MCDataFragment<MCFragment 0x3c74ef0 LayoutOrder:0 Offset:0 HasInstructions:0 BundlePadding:0>
  2286. Contents:[00,00,00,00,00,00,00,00,01,7A,52,00,01,7C,65,01,1B,0C,0D,00] (20 bytes),
  2287. Fixups:[<MCFixup Offset:0 Value:(-)-4 Kind:2>]>,
  2288. <MCAlignFragment<MCFragment 0x3c74fe0 LayoutOrder:1 Offset:20 HasInstructions:0 BundlePadding:0>
  2289. Alignment:4 Value:0 ValueSize:1 MaxBytesToEmit:4>>,
  2290. <MCDataFragment<MCFragment 0x3c75030 LayoutOrder:2 Offset:20 HasInstructions:0 BundlePadding:0>
  2291. Contents:[00,00,00,00,00,00,00,00,00,00,00,00,4A,00,00,00,00,4C,0D,0F,0E,08] (22 bytes),
  2292. Fixups:[<MCFixup Offset:0 Value:(-)-0 Kind:2>,
  2293. <MCFixup Offset:4 Value:(-)-0 Kind:2>,
  2294. <MCFixup Offset:8 Value:- Kind:2>]>,
  2295. <MCAlignFragment<MCFragment 0x3c6ebd0 LayoutOrder:3 Offset:42 HasInstructions:0 BundlePadding:0>
  2296. Alignment:8 Value:0 ValueSize:1 MaxBytesToEmit:8>>,
  2297. <MCDataFragment<MCFragment 0x3c75160 LayoutOrder:4 Offset:48 HasInstructions:0 BundlePadding:0>
  2298. Contents:[] (0 bytes)>]>],
  2299. Symbols:[(.text, Index:0, ),
  2300. (main, Index:0, ),
  2301. (, Index:0, ),
  2302. (, Index:0, ),
  2303. (, Index:0, ),
  2304. (.LBB0_2, Index:0, ),
  2305. (.LBB0_1, Index:0, ),
  2306. (.LBB0_3, Index:0, ),
  2307. (, Index:0, ),
  2308. (, Index:0, ),
  2309. (.comment, Index:0, ),
  2310. (.note.GNU-stack, Index:0, ),
  2311. (.eh_frame, Index:0, ),
  2312. (, Index:0, ),
  2313. (, Index:0, ),
  2314. (, Index:0, ),
  2315. (, Index:0, ),
  2316. (, Index:0, ),
  2317. (, Index:0, )]>
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