module myTask(input logic [0:1] sel, input logic a, input logic b, output logic out);
    always_comb
    begin
        case(sel)
            2'b00: out = (a && b);
            2'b01:
                    begin
                        if(a && !b) out = 0;
                        else out = 1;
                    end
            2'b10: out = (a == b);
            2'b11: out = (a || b);
            default: out = 0;
        endcase
    end
endmodule