module at(clk, clrn, ena, q);
    input clk, clrn, ena;
    output reg[2:0] q;
    always @ (posedge clk or negedge clrn)
    begin
        if(!clrn) q <= 0;
        else
        begin
                q[2]<=ena&(q[2] ^ ~q[1] & ~q[0]);
                q[1]<=ena&(~q[1] ^ q[0]);
                q[0]<=(~q[0]&ena);
        end
    end
endmodule