Working Frequency

main:       ldi     r16,lo8(RAMEND)
            out     SPL,r16
            ldi     r16,hi8(RAMEND)
            out     SPH,r16

            ;PORT B2 = OUTPUT
            ;SUMMER
            sbi DDRB,2

            ;PORTC  0 = INPUT
            ;POT. 1[C0 / ADC0]
            cbi     DDRC,0
            cbi     DDRC,1
            ;PULLUP
            sbi     DDRC,0
            sbi     DDRC,1


            ;Init ADC [ADEN = 1 : Conversion enabled]
            ldi  r16, (1<<ADEN)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)
            out  ADCSR, r16
;------------------------------------------------------------------------
mainloop:   wdr
            ;Channel[0 = ADC0, 1 = ADC1, 2 = ADC2 ...]



            ldi r19,20
            add r19,r1
            mul r19,2
            doit:
                  rcall adco1
                  ldi r16,4
                  out PORTB,r16
                  rcall waitpotims
                  ldi r16,0
                  out PORTB,r16
                  rcall waitpotims

                  dec r19
                  tst r19
                  brne doit

            ldi     ZL,lo8(pot1)
            ldi     ZH,hi8(pot1)
            mov     r25,r1
            rcall   displayTextNumber

            rcall wait500ms

            ldi r19,20
            add r19,r1
            mul r19,2
            doagain:
                  rcall adco2

                  ldi r16,4
                  out PORTB,r16
                  rcall waitpotims
                  ldi r16,0
                  out PORTB,r16
                  rcall waitpotims

                  dec r19
                  tst r19
                  brne doagain

            ldi     ZL,lo8(pot2)
            ldi     ZH,hi8(pot2)
            mov     r25,r1
            rcall   displayTextNumber

            rcall wait500ms


rjmp mainloop

adco1:

            ldi  r16, (1<<REFS0)// set channel
            out  ADMUX, r16
            sbi  ADCSRA, ADSC              // start conversion

            wait_for_conv_finished:
            sbic ADCSRA, ADSC  //bit ADSC goes low after conversion done
            rjmp wait_for_conv_finished

            in   r1, ADCL
            in   r2, ADCH

            ret

adco2:

            ldi  r16, (1<<REFS0) | 1// set channel
            out  ADMUX, r16
            sbi  ADCSRA, ADSC              // start conversion

            wait_for_conv_finished2:
            sbic ADCSRA, ADSC  //bit ADSC goes low after conversion done
            rjmp wait_for_conv_finished2

            in   r1, ADCL
            in   r2, ADCH
            ret


waitpotims: add   r16,r1       ;50 * 10ms = 0,5s
            rcall wait10ms
            ret

wait500ms:  ldi   r16,50       ;50 * 10ms = 0,5s
            rcall wait10ms
            ret

wait10ms:   tst   r16
            breq  wait10msc
            push  r16
            push  r24
            push  r25
wait10ms1:  wdr
            ldi   r24,lo8(3686400/3200)
            ldi   r25,hi8(3686400/3200)
wait10ms2:  sbiw  r24,1
            brne  wait10ms2
            dec   r16
            brne  wait10ms1
            pop   r25
            pop   r24
            pop   r16
wait10msc:  ret


#include "lcd_display.s"
           .text
pot1:      .string  "Pot.1: "
pot2:      .string  "Pot.2: "