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M68000 Assembler 2.83 KB | None | 0 0
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  1. /* aktivnost 1
  2. .equ delayCnt = 9
  3.  
  4. .def tmp=r18
  5.  
  6. .cseg
  7. rjmp reset
  8.  
  9. .org $002
  10. rjmp pali
  11.  
  12. .org $004
  13. rjmp gasi
  14.  
  15. reset:
  16.         ldi tmp, LOW(RAMEND)
  17.         out SPL, tmp
  18.         ldi tmp, HIGH(RAMEND)
  19.         out SPH, tmp
  20.  
  21.         ldi tmp, 0x0F
  22.         out MCUCR, tmp
  23.         ldi tmp, 0b11000000
  24.         out GICR, tmp
  25.         sei
  26.  
  27.         ldi tmp, 0xFF
  28.         out DDRA, tmp
  29.         out PORTA, tmp
  30.  
  31. main:
  32. rjmp main
  33.  
  34. // --------------------------------------------//
  35. // INT0 pali ledice //
  36. pali:
  37.         in r19, PINA
  38.         cpi r19, 0x00
  39.         brne incLed
  40.         ldi r20, 0
  41.  
  42. treptanje1:
  43.         ldi tmp, 0xFF
  44.         out PORTA, tmp
  45.         rcall delay
  46.         ldi tmp, 0x00
  47.         out PORTA, tmp
  48.         rcall delay
  49.         inc r20
  50.         cpi r20, 5
  51.         brne treptanje1
  52.         ldi tmp, 0x00
  53.         out PORTA, tmp
  54.         rjmp kraj1
  55. incLed:
  56.         clc
  57.         rol r19
  58.         out PORTA, r19
  59. kraj1:
  60.         reti
  61.  
  62. // --------------------------------------------//
  63. // INT1 gasi ledice //
  64. gasi:
  65.         in r19, PINA
  66.         cpi r19, 0xFF
  67.         brne decLed
  68.         ldi r20, 0
  69.  
  70. treptanje2:
  71.         ldi tmp, 0b11111110
  72.         out PORTA, tmp
  73.         rcall delay
  74.         ldi tmp, 0b11111111
  75.         out PORTA, tmp
  76.         rcall delay
  77.         inc r20
  78.         cpi r20, 5
  79.         brne treptanje2
  80.         ldi tmp, 0xFF
  81.         out PORTA, tmp
  82.         rjmp kraj2
  83.  
  84. decLed:
  85.         sec
  86.         ror r19
  87.         out PORTA, r19
  88. kraj2:
  89.         reti
  90. // --------------------------------------------//
  91. // delay //
  92. delay:
  93.         clr r23
  94.         clr r24
  95.         ldi r25, delayCnt
  96.         delay_loop:
  97.                 dec r23
  98.                 brne delay_loop
  99.                 dec r24
  100.                 brne delay_loop
  101.                 dec r25
  102.                 brne delay_loop
  103.  
  104.                 ret
  105. */
  106.  
  107. /* aktivnost 2 */
  108. .def tmp=r18
  109. .def tmp2=r19
  110. .def delayCnt=r20
  111.  
  112. .cseg
  113. rjmp reset
  114.  
  115. .org $002
  116. rjmp incFreq
  117.  
  118. .org $004
  119. rjmp decFreq
  120.  
  121. reset:
  122.         ldi tmp, LOW(RAMEND)
  123.         out SPL, tmp
  124.         ldi tmp, HIGH(RAMEND)
  125.         out SPH, tmp
  126.  
  127.         ldi tmp, 0x0F
  128.         out MCUCR, tmp
  129.         ldi tmp, 0b11000000
  130.         out GICR, tmp
  131.         sei
  132.  
  133.         ldi tmp, 0xFF
  134.         out DDRA, tmp
  135.  
  136.         ldi delayCnt, 9
  137.  
  138. main:
  139.         out PORTA, tmp
  140.         rcall delay
  141.         rol tmp
  142. rjmp main
  143.  
  144.  
  145. incFreq:
  146.         ldi tmp2, 255
  147.         cpse delayCnt, tmp2
  148.         inc delayCnt
  149.         reti
  150.  
  151. decFreq:
  152.         ldi tmp2, 1
  153.         cpse delayCnt, tmp2
  154.         dec delayCnt
  155.         reti
  156.  
  157. delay:
  158.         clr r21
  159.         clr r22
  160.         mov r23, delayCnt
  161.         delay_loop:
  162.                 dec r21
  163.                 brne delay_loop
  164.                 dec r22
  165.                 brne delay_loop
  166.                 dec r23
  167.                 brne delay_loop
  168.                 ret
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