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May 29th, 2015
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  1. module imult_ord_radix_4(prod,ready,multiplicand,multiplier,start,clk);
  2.  
  3.    input [15:0]  multiplicand, multiplier;
  4.    input         start, clk;
  5.    output        prod;
  6.    output        ready;
  7.  
  8.    reg [32:0]    product;
  9.    wire [31:0]   prod = product[31:0];
  10.  
  11.    reg [4:0]     bit;
  12.    wire          ready = !bit;
  13.  
  14.    reg [17:0]    pp;
  15.    
  16.    initial bit = 0;
  17.  
  18.    wire [17:0]   multiplicand_X_1 = {1'b0,multiplicand};
  19.    wire [17:0]   multiplicand_X_2 = {multiplicand,1'b0};
  20.    wire [17:0]   multiplicand_X_3 = multiplicand_X_2 + multiplicand_X_1;
  21.  
  22.    always @( posedge clk )
  23.  
  24.      if( ready && start ) begin
  25.  
  26.         bit     = 8;
  27.         product = { 16'd0, multiplier };
  28.        
  29.      end else if( bit ) begin
  30.  
  31.         case ( {product[1:0]} )
  32.           2'd0: pp = {2'b0, product[31:16] };
  33.           2'd1: pp = {2'b0, product[31:16] } + multiplicand_X_1;
  34.           2'd2: pp = {2'b0, product[31:16] } + multiplicand_X_2;
  35.           2'd3: pp = {2'b0, product[31:16] } + multiplicand_X_3;
  36.         endcase
  37.  
  38.         product = { pp, product[15:2] };
  39.         bit     = bit - 1;
  40.  
  41.      end
  42.  
  43. endmodule
  44.  
  45.  
  46. http://www.ece.lsu.edu/ee3755/2002/l07.html
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