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- module imult_ord_radix_4(prod,ready,multiplicand,multiplier,start,clk);
- input [15:0] multiplicand, multiplier;
- input start, clk;
- output prod;
- output ready;
- reg [32:0] product;
- wire [31:0] prod = product[31:0];
- reg [4:0] bit;
- wire ready = !bit;
- reg [17:0] pp;
- initial bit = 0;
- wire [17:0] multiplicand_X_1 = {1'b0,multiplicand};
- wire [17:0] multiplicand_X_2 = {multiplicand,1'b0};
- wire [17:0] multiplicand_X_3 = multiplicand_X_2 + multiplicand_X_1;
- always @( posedge clk )
- if( ready && start ) begin
- bit = 8;
- product = { 16'd0, multiplier };
- end else if( bit ) begin
- case ( {product[1:0]} )
- 2'd0: pp = {2'b0, product[31:16] };
- 2'd1: pp = {2'b0, product[31:16] } + multiplicand_X_1;
- 2'd2: pp = {2'b0, product[31:16] } + multiplicand_X_2;
- 2'd3: pp = {2'b0, product[31:16] } + multiplicand_X_3;
- endcase
- product = { pp, product[15:2] };
- bit = bit - 1;
- end
- endmodule
- http://www.ece.lsu.edu/ee3755/2002/l07.html
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