LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT (Cin, x, y: IN STD_LOGIC;
Cout, s: OUT STD_LOGIC);
END fulladder;
ARCHITECTURE equations OF fulladder IS
BEGIN
s<= x XOR y XOR Cin;
Cout <= (x AND y) OR (x AND Cin) OR (y AND Cin);
END equations;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY adder IS
PORT (Cin : IN STD_LOGIC;
X, Y: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Cout : OUT STD_LOGIC);
END adder;
ARCHITECTURE structure OF adder IS
SIGNAL C:STD_LOGIC_VECTOR (1 TO 3);
COMPONENT fulladder IS
PORT (Cin, x, y: IN STD_LOGIC;
Cout, s: OUT STD_LOGIC);
END COMPONENT;
BEGIN
stage0: fulladder PORT MAP (Cin, X(0), Y(0), C(1), S(0));
stage1: fulladder PORT MAP (C(1), X(1), Y(1), C(2), S(1));
stage2: fulladder PORT MAP (C(2), X(2), Y(2), C(3), S(2));
stage3: fulladder PORT MAP (C(3), X(3), Y(3), Cout, S(3));
END structure;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY addsub IS
PORT (CTL : IN STD_LOGIC;
A, B: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Cout : OUT STD_LOGIC);
END addsub;
ARCHITECTURE structure OF addsub IS
SIGNAL mult:STD_LOGIC_VECTOR (0 TO 3);
COMPONENT adder IS
PORT (Cin : IN STD_LOGIC;
x, y: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Cout : OUT STD_LOGIC);
END COMPONENT;
BEGIN
mult <= B when (CTL = '1') else NOT B;
stage0: adder PORT MAP (CTL, A, mult, S, Cout);
END structure;