# (c) Xilinx

# 1. Check that the Vivado objects are valid. Generate a TCL_ERROR otherwise (revised)

proc get_pin_dir { pinName } {
    if {$pinName == {}} {
        error "Error - no pin name provided"
    }
    set pin [get_pins $pinName]
    if {$pin == {}} {
        error "Error - pin $pinName does not exist"
    }
    set direction [get_property DIRECTION $pin]
    return $direction
}

# 2. Creating custom design rules checks (DRCs)

# This is simplistic check -- report BRAM cells with WRITE_WIDTH_B wider than 36
proc dataWidthCheck {} {
    # list to hold violations
    set vios {}
    # iterate through the objects to be checked
    foreach bram [get_cells -hier -filter {PRIMITIVE_SUBGROUP == bram}] {
        set bwidth [get_property WRITE_WIDTH_B $bram]
        if {$bwidth > 36} {
            #define the message to report when violations are found
            set msg "On cell %ELG, WRITE_WIDTH_B is $bwidth"
            set vio [ create_drc_violation -name {RAMW-1} -msg $msg $bram ]
            lappend vios $vio
            }; #end IF
        }; # end FOR
    if {[llength $vios] > 0} {
        return -code error $vios
    } else {
        return {}
    }; #end IF
}; #end PROC


# DRC explanation script
proc explain_drc {drcs} {
    package require struct::matrix
    set loop_drcs [get_drc_checks $drcs]
    if {$loop_drcs == {}} {
        puts "Error : $drcs does not match any existing DRC rule"
        return
    }

    struct::matrix drcsm
    drcsm add colums 3
    drcsm add row {DRC_ID SEVERITY DESCRIPTION}
    foreach drc $loop_drcs {
        set description "\{[get_property NAME {get_drc_checks $drc]]\}"
        set severity "\{[get_property SEVERITY [get_drc_checks $drc]]\}"
        set key "\{[get_property KEY [get_drc_checks $drc]]\}"
        drcsm add row "$key $severity $description"
    }
    puts "[drcsm format 2chan]";
    drcsm destroy
}