Timing constraint: TS_rx_clk_in_n = PERIOD TIMEGRP "rx_clk_in_n" 246 MHz HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 72955 paths analyzed, 24062 endpoints analyzed, 67 failing endpoints
 67 timing errors detected. (67 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   4.750ns.
--------------------------------------------------------------------------------
Slack:                  -0.685ns (requirement - (data path - clock path skew + uncertainty))
  Source:               axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram (RAM)
  Destination:          axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/fwd_data_42 (FF)
  Requirement:          4.065ns
  Data Path Delay:      4.323ns (Levels of Logic = 1)
  Clock Path Skew:      -0.392ns (1.342 - 1.734)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.065ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram to axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/fwd_data_42
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X2Y20.DOBDO10 Trcko_DOB             2.454   axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram
                                                       axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram
    SLICE_X32Y101.B4     net (fanout=1)        0.985   axi_dmac_1/axi_dmac_1/i_request_arb/dest_fifo_data<42>
    SLICE_X32Y101.BMUX   Tilo                  0.374   axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/bwd_data<43>
                                                       axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/Mmux_bwd_data_s371
    SLICE_X32Y99.AX      net (fanout=2)        0.494   axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/bwd_data_s<42>
    SLICE_X32Y99.CLK     Tdick                 0.016   axi_dmac_1_fifo_rd_dout<42>
                                                       axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/fwd_data_42
    -------------------------------------------------  ---------------------------
    Total                                      4.323ns (2.844ns logic, 1.479ns route)
                                                       (65.8% logic, 34.2% route)