library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
port(  clk_input:  in std_logic;
  reset:  in std_logic;
  enable:  in std_logic;
  count:  out std_logic_vector(3 downto 0)
);
end counter;

architecture behav of counter is

signal pre_count: std_logic_vector(3 downto 0);
signal clk_divider : std_logic_vector(23 downto 0) := x"000000";
signal slow_clk : std_logic;


  begin

  clk_division : process (clk_input, clk_divider)
    begin
        if (clk_input = '1' and clk_input'event) then
            clk_divider <= clk_divider + 1;
        end if;
        slow_clk <= clk_divider(23);
        end process;

    counting: process(slow_clk, enable, reset)
    begin

     if reset = '1' then
        pre_count <= "0000";
      elsif rising_edge(slow_clk) then
        if enable = '1' then
          pre_count <= pre_count + '1';
        end if;
      end if;
    end process;
    count <= pre_count;
end behav;