[CHIPSEC] Executing command 'mmio' with args ['list']


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 MMIO Range   | BAR Register   | Base             | Size     | En? | Description
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 GTTMMADR     | 00:02.0 + 0x10 | 00000000DE000000 | 00001000 | 1   | Graphics Translation Table Range
 GFXVTBAR     | GFXVTBAR       | 00000000FED90000 | 00001000 | 1   | Intel Processor Graphics VT-d Register Range
 SPIBAR       | 00:1F.5 + 0x10 | 00000000FE010000 | 00001000 | 1   | SPI Controller Register Range
 HDABAR       | 00:1F.3 + 0x10 | 00000000DF140000 | 00001000 | 1   | HD Audio Base
 GMADR        | 00:02.0 + 0x18 | 00000000C0000000 | 00001000 | 1   | Graphics Memory Range
 DMIBAR       | 00:00.0 + 0x68 | 00000000FED18000 | 00001000 | 1   | Root Complex Register Range
 MMCFG        | 00:00.0 + 0x60 | 00000000E0000000 | 00001000 | 1   | PCI Express Register Range
 RCBA         | 00:1F.0 + 0xF0 | 0000000000000000 | 00004000 | 0   | PCH Root Complex Register Range
 VTBAR        | VTBAR          | 00000000FED91000 | 00001000 | 1   | Intel VT-d Register Register Range
 MCHBAR       | 00:00.0 + 0x48 | 00000000FED10000 | 00008000 | 1   | Host Memory Mapped Register Range
 PXPEPBAR     | 00:00.0 + 0x40 | 00000000FED19000 | 00001000 | 1   | PCI Express Egress Port Register Range
 RCBA_RTC     | 00:1F.0 + 0xF0 | 0000000000003400 | 00000200 | 0   | General Control Register Range
 HDBAR        | 00:1B.0 + 0x10 | 0000007FFFFFC000 | 00001000 | 1   | PCH HD Audio Controller Register Range