module PosEdgeDFF(clk, data, clr, Q, Qnot);

    input clk, data, clr;   //clr is active low;
    output Q, Qnot;

    wire w1, w2, w3, w4, w5;

    nand(w1, w4, w2);
    nand(w2, w1, clr, clk);
    nand(w3, w2, clk, w4);
    nand(w4, w3, clr, data);

    nand(Q, w2, Qnot);
    nand(Qnot, w3, clr, Q);

endmodule

`timescale 1ns/1ps
module PosEdgeDFF_tb();

    reg clk, data, clr;
    wire Q, Qnot;
    PosEdgeDFF uut(clk, data, clr, Q, Qnot);

    always begin
        #5 clk = ~clk;
    end

    always begin
        #1 data = ~data;
    end

    initial begin
        clk = 0;
        data = 0;
        clr = 0;
        #1;
        clr = 1;
        #80;
        $finish;
    end
endmodule