library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity A1 is
Port (Clk : in  STD_LOGIC; --GCLK0 (V10)
	x : in  STD_LOGIC;--SW7   (T5)
	T : in  STD_LOGIC;
  --BTND  (C9)
  R : in  STD_LOGIC;
  --SW6   (V8)
  z1 : out STD_LOGIC;
  --LD7   (T11)
  z2 : out STD_LOGIC);
  --LD6   (R11)
  end A1;
  architecture Behavioral of A1 is
  component divider is
  Port (     Clk : in    STD_LOGIC;
  Clk_div : inout STD_LOGIC := '0');
  end component divider;
  component impuls is
  Port( Clk_div, T : in STD_LOGIC;
  C : buffer STD_LOGIC);
  end component impuls;
  component NAND4 is
  Port(a,b,c,d : in STD_LOGIC:='1';
  z : out STD_LOGIC);
end component NAND4;
component FFD is
Port(D, C, R  : in STD_LOGIC;
Q, nQ : out STD_LOGIC);
end component FFD;
signal Clk_div,C, nx, Q1,Q2,nQ1,nQ2, v1,v2,v3,v4, D1,D2 : STD_LOGIC;
begin
c1: divider port map (Clk, Clk_div);
c2: impuls  port map(Clk_div, T, C);
 b0: NAND4   port map (a => x, z => nx);
 b1: NAND4   port map (nQ1, Q2, nx, '1', v1);
 b2: NAND4   port map (Q1, nQ2, nx, '1', v2);
 b3: NAND4   port map (nQ1, nQ2, x, '1', v3);
 b4: NAND4   port map (Q1, Q2, x, '1', v4);
 b5: NAND4   port map (v1, v2, v3, v4, D1);D2 <= nQ2;
 p1: FFD     port map (D1, C, R, Q1, nQ1);
 p2: FFD     port map (D2, C, R, Q2, nQ2);
 b6: NAND4 port map (nQ1, nQ2, '1', '1', z1); z2 <=  Q2;
 end Behavioral;