hmsclock

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hmsclock is
    Port ( Clk : in  STD_LOGIC;
           En : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Cout : out  STD_LOGIC;
           Hours : out  STD_LOGIC_VECTOR (4 downto 0);
           Minutes : out  STD_LOGIC_VECTOR (5 downto 0);
           Seconds : out  STD_LOGIC_VECTOR (5 downto 0));
end hmsclock;

architecture Behavioral of hmsclock is

signal SCOUT, MCOUT: STD_LOGIC;

component Counter_60 port (
    Clk : in  STD_LOGIC;
    En : in  STD_LOGIC;
    Rst : in  STD_LOGIC;
    Cout : out  STD_LOGIC;
    Fout : out  STD_LOGIC_VECTOR (5 downto 0));
end component;

component Counter_24 port (
    Clk : in  STD_LOGIC;
    En : in  STD_LOGIC;
    Rst : in  STD_LOGIC;
    Cout : out  STD_LOGIC;
    Fout : out  STD_LOGIC_VECTOR (4 downto 0));
end component;

begin

SecondsCounter: Counter_60 port map(
    Clk => Clk,
    En => En,
    Rst => Rst,
    Fout => Seconds,
    Cout => SCOUT
);

MinutesCounter: Counter_60 port map(
    Clk => SCOUT,
    En => En,
    Rst => Rst,
    Fout => Minutes,
    Cout => MCOUT
);

HoursCounter: Counter_24 port map(
    Clk => MCOUT,
    En => En,
    Rst => Rst,
    Fout => Hours,
    Cout => Cout
);

end Behavioral;