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  1. commit 378f7453100e676b6cb6a862db2aad7f04dceaa6
  2. Author: Marcin Bukat <marcin.bukat@gmail.com>
  3. Date: Thu Jul 18 23:55:35 2013 +0200
  4.  
  5. hwstub rk27xx port WIP
  6.  
  7. Change-Id: I85ac57117911544b65ccd56eb16303e30be67cab
  8.  
  9. diff --git a/utils/hwstub/hwstub_protocol.h b/utils/hwstub/hwstub_protocol.h
  10. index 99131aa..dc4c52f 100644
  11. --- a/utils/hwstub/hwstub_protocol.h
  12. +++ b/utils/hwstub/hwstub_protocol.h
  13. @@ -101,6 +101,7 @@ struct usb_resp_info_features_t
  14.  
  15. #define HWSTUB_TARGET_UNK ('U' | 'N' << 8 | 'K' << 16 | ' ' << 24)
  16. #define HWSTUB_TARGET_STMP ('S' | 'T' << 8 | 'M' << 16 | 'P' << 24)
  17. +#define HWSTUB_TARGET_RK27 ('R' | 'K' << 8 | '2' << 16 | '7' << 24)
  18.  
  19. struct usb_resp_info_target_t
  20. {
  21. diff --git a/utils/hwstub/stub/SOURCES b/utils/hwstub/stub/SOURCES
  22. index bfb847c..af33711 100644
  23. --- a/utils/hwstub/stub/SOURCES
  24. +++ b/utils/hwstub/stub/SOURCES
  25. @@ -9,4 +9,7 @@ format.c
  26. #ifdef CONFIG_STMP
  27. usb_drv_arc.c
  28. stmp/target.c
  29. +#elif defined(CONFIG_RK27XX)
  30. +rk27xx/usb_drv_rk27xx.c
  31. +rk27xx/target.c
  32. #endif
  33. diff --git a/utils/hwstub/stub/rk27xx/Makefile b/utils/hwstub/stub/rk27xx/Makefile
  34. new file mode 100644
  35. index 0000000..9731a44
  36. --- /dev/null
  37. +++ b/utils/hwstub/stub/rk27xx/Makefile
  38. @@ -0,0 +1,14 @@
  39. +#
  40. +# common
  41. +#
  42. +CC=arm-elf-eabi-gcc
  43. +LD=arm-elf-eabi-gcc
  44. +AS=arm-elf-eabi-gcc
  45. +OC=arm-elf-eabi-objcopy
  46. +DEFINES=
  47. +INCLUDES=-I$(CURDIR)
  48. +GCCOPTS=-march=armv5te
  49. +BUILD_DIR=$(CURDIR)/build/
  50. +ROOT_DIR=$(CURDIR)/..
  51. +
  52. +include ../hwstub.make
  53. diff --git a/utils/hwstub/stub/rk27xx/rk27xx.h b/utils/hwstub/stub/rk27xx/rk27xx.h
  54. new file mode 100644
  55. index 0000000..8be5ce4
  56. --- /dev/null
  57. +++ b/utils/hwstub/stub/rk27xx/rk27xx.h
  58. @@ -0,0 +1,1158 @@
  59. +/* ARM part only for now */
  60. +#define AHB_SRAM 0x00000000
  61. +
  62. +#define ARM_BUS0_BASE 0x18000000
  63. +#define ARM_BUS1_BASE 0x18400000
  64. +
  65. +#define FLASH_BANK0 0x10000000
  66. +#define FLASH_BANK1 0x11000000
  67. +
  68. +/* Timers */
  69. +#define APB0_TIMER (ARM_BUS0_BASE + 0x00000000)
  70. +#define TMR0LR (*(volatile unsigned long *)(APB0_TIMER + 0x00))
  71. +#define TMR0CVR (*(volatile unsigned long *)(APB0_TIMER + 0x04))
  72. +#define TMR0CON (*(volatile unsigned long *)(APB0_TIMER + 0x08))
  73. +
  74. +#define TMR1LR (*(volatile unsigned long *)(APB0_TIMER + 0x10))
  75. +#define TMR1CVR (*(volatile unsigned long *)(APB0_TIMER + 0x14))
  76. +#define TMR1CON (*(volatile unsigned long *)(APB0_TIMER + 0x18))
  77. +
  78. +#define TMR2LR (*(volatile unsigned long *)(APB0_TIMER + 0x20))
  79. +#define TMR2CVR (*(volatile unsigned long *)(APB0_TIMER + 0x24))
  80. +#define TMR2CON (*(volatile unsigned long *)(APB0_TIMER + 0x28))
  81. +
  82. +/* UART0 */
  83. +#define APB0_UART0 (ARM_BUS0_BASE + 0x00004000)
  84. +#define UART0_RBR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
  85. +#define UART0_THR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
  86. +#define UART0_DLL (*(volatile unsigned long *)(APB0_UART0 + 0x00))
  87. +#define UART0_DLH (*(volatile unsigned long *)(APB0_UART0 + 0x04))
  88. +#define UART0_IER (*(volatile unsigned long *)(APB0_UART0 + 0x04))
  89. +#define UART0_IIR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
  90. +#define UART0_FCR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
  91. +#define UART0_LCR (*(volatile unsigned long *)(APB0_UART0 + 0x0C))
  92. +#define UART0_MCR (*(volatile unsigned long *)(APB0_UART0 + 0x10))
  93. +#define UART0_LSR (*(volatile unsigned long *)(APB0_UART0 + 0x14))
  94. +#define UART0_MSR (*(volatile unsigned long *)(APB0_UART0 + 0x18))
  95. +
  96. +/* UART1 */
  97. +#define APB0_UART1 (ARM_BUS0_BASE + 0x00008000)
  98. +#define UART1_RBR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
  99. +#define UART1_THR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
  100. +#define UART1_DLL (*(volatile unsigned long *)(APB0_UART1 + 0x00))
  101. +#define UART1_DLH (*(volatile unsigned long *)(APB0_UART1 + 0x04))
  102. +#define UART1_IER (*(volatile unsigned long *)(APB0_UART1 + 0x04))
  103. +#define UART1_IIR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
  104. +#define UART1_FCR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
  105. +#define UART1_LCR (*(volatile unsigned long *)(APB0_UART1 + 0x0C))
  106. +#define UART1_MCR (*(volatile unsigned long *)(APB0_UART1 + 0x10))
  107. +#define UART1_LSR (*(volatile unsigned long *)(APB0_UART1 + 0x14))
  108. +#define UART1_MSR (*(volatile unsigned long *)(APB0_UART1 + 0x18))
  109. +
  110. +/* GPIO ports A,B,C,D */
  111. +#define APB0_GPIO0 (ARM_BUS0_BASE + 0x0000C000)
  112. +#define GPIO_PADR (*(volatile unsigned long *)(APB0_GPIO0 + 0x00))
  113. +#define GPIO_PACON (*(volatile unsigned long *)(APB0_GPIO0 + 0x04))
  114. +#define GPIO_PBDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x08))
  115. +#define GPIO_PBCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x0C))
  116. +#define GPIO_PCDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x10))
  117. +#define GPIO_PCCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x14))
  118. +#define GPIO_PDDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x18))
  119. +#define GPIO_PDCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x1C))
  120. +#define GPIO_TEST (*(volatile unsigned long *)(APB0_GPIO0 + 0x20))
  121. +#define GPIO_IEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x24))
  122. +#define GPIO_IEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x28))
  123. +#define GPIO_IEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x2C))
  124. +#define GPIO_IED (*(volatile unsigned long *)(APB0_GPIO0 + 0x30))
  125. +#define GPIO_ISA (*(volatile unsigned long *)(APB0_GPIO0 + 0x34))
  126. +#define GPIO_ISB (*(volatile unsigned long *)(APB0_GPIO0 + 0x38))
  127. +#define GPIO_ISC (*(volatile unsigned long *)(APB0_GPIO0 + 0x3C))
  128. +#define GPIO_ISD (*(volatile unsigned long *)(APB0_GPIO0 + 0x40))
  129. +#define GPIO_IBEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x44))
  130. +#define GPIO_IBEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x48))
  131. +#define GPIO_IBEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x4C))
  132. +#define GPIO_IBED (*(volatile unsigned long *)(APB0_GPIO0 + 0x50))
  133. +#define GPIO_IEVA (*(volatile unsigned long *)(APB0_GPIO0 + 0x54))
  134. +#define GPIO_IEVB (*(volatile unsigned long *)(APB0_GPIO0 + 0x58))
  135. +#define GPIO_IEVC (*(volatile unsigned long *)(APB0_GPIO0 + 0x5C))
  136. +#define GPIO_IEVD (*(volatile unsigned long *)(APB0_GPIO0 + 0x60))
  137. +#define GPIO_ICA (*(volatile unsigned long *)(APB0_GPIO0 + 0x64))
  138. +#define GPIO_ICB (*(volatile unsigned long *)(APB0_GPIO0 + 0x68))
  139. +#define GPIO_ICC (*(volatile unsigned long *)(APB0_GPIO0 + 0x6C))
  140. +#define GPIO_ICD (*(volatile unsigned long *)(APB0_GPIO0 + 0x70))
  141. +#define GPIO_ISR (*(volatile unsigned long *)(APB0_GPIO0 + 0x74))
  142. +
  143. +/* Watchdog */
  144. +#define APB0_WDT (ARM_BUS0_BASE + 0x00010000)
  145. +#define WDTLR (*(volatile unsigned long *)(APB0_WDT + 0x00))
  146. +#define WDTCVR (*(volatile unsigned long *)(APB0_WDT + 0x04))
  147. +#define WDTCON (*(volatile unsigned long *)(APB0_WDT + 0x08))
  148. +
  149. +/* RTC module documentation missing */
  150. +#define APB0_RTC (ARM_BUS0_BASE + 0x00014000)
  151. +#define RTC_TIME (*(volatile unsigned long *)(APB0_RTC + 0x00))
  152. +#define RTC_DATE (*(volatile unsigned long *)(APB0_RTC + 0x04))
  153. +#define RTC_TALARM (*(volatile unsigned long *)(APB0_RTC + 0x08))
  154. +#define RTC_DALARM (*(volatile unsigned long *)(APB0_RTC + 0x0C))
  155. +#define RTC_CTRL (*(volatile unsigned long *)(APB0_RTC + 0x10))
  156. +#define RTC_RESET (*(volatile unsigned long *)(APB0_RTC + 0x14))
  157. +#define RTC_PWOFF (*(volatile unsigned long *)(APB0_RTC + 0x18))
  158. +#define RTC_PWFAIL (*(volatile unsigned long *)(APB0_RTC + 0x1C))
  159. +
  160. +/* SPI */
  161. +#define APB0_SPI (ARM_BUS0_BASE + 0x00018000)
  162. +#define SPI_TXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
  163. +#define SPI_RXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
  164. +#define SPI_IER (*(volatile unsigned long *)(APB0_SPI + 0x04))
  165. +#define SPI_FCR (*(volatile unsigned long *)(APB0_SPI + 0x08))
  166. +#define SPI_FWCR (*(volatile unsigned long *)(APB0_SPI + 0x0C))
  167. +#define SPI_DLYCR (*(volatile unsigned long *)(APB0_SPI + 0x10))
  168. +#define SPI_TXCR (*(volatile unsigned long *)(APB0_SPI + 0x14))
  169. +#define SPI_RXCR (*(volatile unsigned long *)(APB0_SPI + 0x18))
  170. +#define SPI_SSCR (*(volatile unsigned long *)(APB0_SPI + 0x1C))
  171. +#define SPI_ISR (*(volatile unsigned long *)(APB0_SPI + 0x20))
  172. +
  173. +/* SCU module */
  174. +#define APB0_SCU (ARM_BUS0_BASE + 0x0001C000)
  175. +#define SCU_ID (*(volatile unsigned long *)(APB0_SCU + 0x00))
  176. +#define SCU_REMAP (*(volatile unsigned long *)(APB0_SCU + 0x04))
  177. +#define SCU_PLLCON1 (*(volatile unsigned long *)(APB0_SCU + 0x08))
  178. +#define SCU_PLLCON2 (*(volatile unsigned long *)(APB0_SCU + 0x0C))
  179. +#define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10))
  180. +#define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14))
  181. +#define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18))
  182. +#define CLKCFG_OTP (1<<0)
  183. +#define CLKCFG_DSP (1<<1)
  184. +#define CLKCFG_SDRAM (1<<2)
  185. +#define CLKCFG_HDMA (1<<3)
  186. +#define CLKCFG_DWDMA (1<<4)
  187. +#define CLKCFG_UHC (1<<5)
  188. +#define CLKCFG_UDC (1<<6)
  189. +/* 7 - 8 reserved */
  190. +#define CLKCFG_NAND (1<<9)
  191. +#define CLKCFG_A2A (1<<10)
  192. +#define CLKCFG_SRAM (1<<11)
  193. +#define CLKCFG_HCLK_LCDC (1<<12)
  194. +#define CLKCFG_LCDC (1<<13)
  195. +#define CLKCFG_HCLK_VIP (1<<14)
  196. +#define CLKCFG_VIP (1<<15)
  197. +#define CLKCFG_I2S (1<<16)
  198. +#define CLKCFG_PCLK_I2S (1<<17)
  199. +#define CLKCFG_UART0 (1<<18)
  200. +#define CLKCFG_UART1 (1<<19)
  201. +#define CLKCFG_I2C (1<<20)
  202. +#define CLKCFG_SPI (1<<21)
  203. +#define CLKCFG_SD (1<<22)
  204. +#define CLKCFG_PCLK_LSADC (1<<23)
  205. +#define CLKCFG_LSADC (1<<24)
  206. +#define CLKCFG_HCLK_HSADC (1<<25)
  207. +#define CLKCFG_HSADC (1<<26)
  208. +#define CLKCFG_GPIO (1<<27)
  209. +#define CLKCFG_TIMER (1<<28)
  210. +#define CLKCFG_PWM (1<<29)
  211. +#define CLKCFG_RTC (1<<30)
  212. +#define CLKCFG_WDT (1<<31)
  213. +
  214. +#define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C))
  215. +#define RSTCFG_UHC (1<<0)
  216. +#define RSTCFG_UDC (1<<1)
  217. +#define RSTCFG_LCDC (1<<2)
  218. +#define RSTCFG_VIP (1<<3)
  219. +#define RSTCFG_DSP_CORE (1<<4)
  220. +#define RSTCFG_DSP_PERI (1<<5)
  221. +#define RSTCFG_CODEC (1<<6)
  222. +#define RSTCFG_LSADC (1<<7)
  223. +#define RSTCFG_HSADC (1<<8)
  224. +#define RSTCFG_SD (1<<9)
  225. +#define RSTCFG_MAILBOX (1<<10)
  226. +#define RSTCFG_ECT (1<<11)
  227. +#define RSTCFG_ARM_CORE (1<<12)
  228. +/* 13 - 31 reserved */
  229. +
  230. +#define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20))
  231. +#define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24))
  232. +#define SCU_CHIPCFG (*(volatile unsigned long *)(APB0_SCU + 0x28))
  233. +#define SCU_STATUS (*(volatile unsigned long *)(APB0_SCU + 0x2C))
  234. +#define SCU_IOMUXA_CON (*(volatile unsigned long *)(APB0_SCU + 0x30))
  235. +/* 20 - 31 reserved */
  236. +#define IOMUX_I2S_PAD (1<<19)
  237. +#define IOMUX_I2S_CODEC (0<<19)
  238. +#define IOMUX_I2C_PAD (1<<18)
  239. +#define IOMUX_I2C_CODEC (0<<18)
  240. +#define IOMUX_GPIO_B7 (2<<16)
  241. +#define IOMUX_NAND_CS3 (1<<16)
  242. +#define IOMUX_I2C_SDA (0<<16)
  243. +#define IOMUX_GPIO_B6 (2<<14)
  244. +#define IOMUX_NAND_CS2 (1<<14)
  245. +#define IOMUX_I2C_SCL (0<<14)
  246. +#define IOMUX_SPI (2<<12)
  247. +#define IOMUX_SD (1<<12)
  248. +#define IOMUX_GPIO_B05 (0<<12)
  249. +#define IOMUX_LCD_VSYNC (1<<11)
  250. +#define IOMUX_GPIO_A7 (0<<11)
  251. +#define IOMUX_LCD_DEN (1<<10)
  252. +#define IOMUX_GPIO_A6 (0<<10)
  253. +#define IOMUX_NAND_CS1 (1<<9)
  254. +#define IOMUX_GPIO_A5 (0<<9)
  255. +#define IOMUX_LCD_D22 (1<<8)
  256. +#define IOMUX_GPIO_A4 (0<<8)
  257. +#define IOMUX_UART0_NRTS (2<<6)
  258. +#define IOMUX_LCD_D20 (1<<6)
  259. +#define IOMUX_GPIO_A3 (0<<6)
  260. +#define IOMUX_UART0_NCTS (2<<4)
  261. +#define IOMUX_LCD_D18 (1<<4)
  262. +#define IOMUX_GPIO_A2 (0<<4)
  263. +#define IOMUX_UART0_TXD (2<<2)
  264. +#define IOMUX_LCD_D17 (1<<2)
  265. +#define IOMUX_GPIO_A1 (0<<2)
  266. +#define IOMUX_UART0_RXD (2<<0)
  267. +#define IOMUX_LCD_D16 (1<<0)
  268. +#define IOMUX_GPIO_A0 (0<<0)
  269. +
  270. +#define SCU_IOMUXB_CON (*(volatile unsigned long *)(APB0_SCU + 0x34))
  271. +/* bits 31 - 23 reserved */
  272. +#define IOMUX_HADC (1<<22)
  273. +#define IOMUX_VIP (0<<22)
  274. +#define IOMUX_SDRAM_CKE (1<<21)
  275. +#define IOMUX_GPIO_D3 (0<<21)
  276. +#define IOMUX_UHC_VBUS (1<<20)
  277. +#define IOMUX_GPIO_F4 (0<<20)
  278. +#define IOMUX_UHC_OCUR (1<<19)
  279. +#define IOMUX_GPIO_F3 (0<<19)
  280. +#define IOMUX_GPIO_F2 (1<<18)
  281. +#define IOMUX_SDRAM_A12 (0<<18)
  282. +#define IOMUX_GPIO_F1 (1<<17)
  283. +#define IOMUX_SDRAM_A11 (0<<17)
  284. +#define IOMUX_VIP_CLK (1<<16)
  285. +#define IOMUX_GPIO_F0 (0<<16)
  286. +#define IOMUX_LCD_D815 (1<<15)
  287. +#define IOMUX_GPIO_E07 (0<<15)
  288. +#define IOMUX_PWM3 (1<<14)
  289. +#define IOMUX_GPIO_D7 (0<<14)
  290. +#define IOMUX_PWM2 (1<<13)
  291. +#define IOMUX_GPIO_D6 (0<<13)
  292. +#define IOMUX_PWM1 (1<<12)
  293. +#define IOMUX_GPIO_D5 (0<<12)
  294. +#define IOMUX_PWM0 (1<<11)
  295. +#define IOMUX_GPIO_D4 (0<<11)
  296. +#define IOMUX_SD_WPA (1<<10)
  297. +#define IOMUX_GPIO_D2 (0<<10)
  298. +#define IOMUX_UART1_RXD (2<<8)
  299. +#define IOMUX_SD_CDA (1<<8)
  300. +#define IOMUX_GPIO_D1 (0<<8)
  301. +#define IOMUX_UART1_TXD (2<<6)
  302. +#define IOMUX_SD_PCA (1<<6)
  303. +#define IOMUX_GPIO_D0 (0<<6)
  304. +#define IOMUX_STMEM_CS1 (1<<5)
  305. +#define IOMUX_GPIO_C7 (0<<5)
  306. +#define IOMUX_I2S_CLK (1<<4)
  307. +#define IOMUX_GPIO_C6 (0<<4)
  308. +#define IOMUX_I2S_SDO (1<<3)
  309. +#define IOMUX_GPIO_C5 (0<<3)
  310. +#define IOMUX_I2S_SDI (1<<2)
  311. +#define IOMUX_GPIO_C4 (0<<2)
  312. +#define IOMUX_I2S_LRCK (1<<1)
  313. +#define IOMUX_GPIO_C3 (0<<1)
  314. +#define IOMUX_I2S_SCLK (1<<0)
  315. +#define IOMUX_GPIO_C2 (0<<0)
  316. +
  317. +#define SCU_GPIOUPCON (*(volatile unsigned long *)(APB0_SCU + 0x38))
  318. +#define SCU_DIVCON2 (*(volatile unsigned long *)(APB0_SCU + 0x3C))
  319. +
  320. +/* I2C controller */
  321. +#define APB0_I2C (ARM_BUS0_BASE + 0x00020000)
  322. +#define I2C_MTXR (*(volatile unsigned long *)(APB0_I2C + 0x00))
  323. +#define I2C_MRXR (*(volatile unsigned long *)(APB0_I2C + 0x04))
  324. +#define I2C_STXR (*(volatile unsigned long *)(APB0_I2C + 0x08))
  325. +#define I2C_SRXR (*(volatile unsigned long *)(APB0_I2C + 0x0C))
  326. +#define I2C_SADDR (*(volatile unsigned long *)(APB0_I2C + 0x10))
  327. +#define I2C_IER (*(volatile unsigned long *)(APB0_I2C + 0x14))
  328. +#define I2C_ISR (*(volatile unsigned long *)(APB0_I2C + 0x18))
  329. +#define I2C_LCMR (*(volatile unsigned long *)(APB0_I2C + 0x1C))
  330. +#define I2C_LSR (*(volatile unsigned long *)(APB0_I2C + 0x20))
  331. +#define I2C_CONR (*(volatile unsigned long *)(APB0_I2C + 0x24))
  332. +#define I2C_OPR (*(volatile unsigned long *)(APB0_I2C + 0x28))
  333. +
  334. +/* SD card controller */
  335. +#define APB0_SD (ARM_BUS0_BASE + 0x00024000)
  336. +#define MMU_CTRL (*(volatile unsigned long *)(APB0_SD + 0x00))
  337. +#define MMU_BIG_ENDIAN (1<<12)
  338. +#define MMU_DMA_START (1<<11)
  339. +#define MMU_DMA_WRITE (1<<10)
  340. +#define MMU_MMU0_BUFI (0<<9)
  341. +#define MMU_MMU0_BUFII (1<<9)
  342. +#define MMU_CPU_BUFI (0<<8)
  343. +#define MMU_CPU_BUFII (1<<8)
  344. +#define MMU_BUFII_RESET (1<<7)
  345. +#define MMU_BUFII_END (1<<6)
  346. +#define MMU_BUFII_BYTE (0<<4)
  347. +#define MMU_BUFII_HALFWORD (1<<4)
  348. +#define MMU_BUFII_WORD (3<<4)
  349. +#define MMU_BUFI_RESET (1<<3)
  350. +#define MMU_BUFI_END (1<<2)
  351. +#define MMU_BUFI_BYTE (0<<0)
  352. +#define MMU_BUFI_HALFWORD (1<<0)
  353. +#define MMU_BUFI_WORD (3<<0)
  354. +
  355. +#define MMU_PNRI (*(volatile unsigned long *)(APB0_SD + 0x04))
  356. +#define CUR_PNRI (*(volatile unsigned long *)(APB0_SD + 0x08))
  357. +#define MMU_PNRII (*(volatile unsigned long *)(APB0_SD + 0x0C))
  358. +#define CUR_PNRII (*(volatile unsigned long *)(APB0_SD + 0x10))
  359. +#define MMU_ADDR (*(volatile unsigned long *)(APB0_SD + 0x14))
  360. +#define CUR_ADDR (*(volatile unsigned long *)(APB0_SD + 0x18))
  361. +#define MMU_DATA (*(volatile unsigned long *)(APB0_SD + 0x1C))
  362. +
  363. +#define SD_CTRL (*(volatile unsigned long *)(APB0_SD + 0x20))
  364. +#define SD_PWR_CD (1<<13)
  365. +#define SD_PWR_CPU (0<<13)
  366. +#define SD_DETECT_CDDAT3 (1<<12)
  367. +#define SD_DETECT_MECH (0<<12)
  368. +#define SD_CLOCK_DIS (1<<11)
  369. +#define SD_CLOCK_EN (0<<11)
  370. +#define SD_DIV(x) ((x)&0x7ff)
  371. +
  372. +#define SD_INT (*(volatile unsigned long *)(APB0_SD + 0x24))
  373. +#define CMD_RES_STAT (1<<6)
  374. +#define DATA_XFER_STAT (1<<5)
  375. +#define CD_DETECT_STAT (1<<4)
  376. +#define CMD_RES_INT_EN (1<<2)
  377. +#define DATA_XFER_INT_EN (1<<1)
  378. +#define CD_DETECT_IN_EN (1<<0)
  379. +
  380. +#define SD_CARD (*(volatile unsigned long *)(APB0_SD + 0x28))
  381. +#define SD_CARD_SELECT (1<<7)
  382. +#define SD_CARD_PWR_EN (1<<6)
  383. +#define SD_CARD_DETECT_INT_EN (1<<5)
  384. +#define SD_CARD_BSY (1<<2)
  385. +#define SD_CARD_WRITE_PROTECT (1<<1)
  386. +#define SD_CARD_DETECT (1<<0)
  387. +
  388. +#define SD_CMDREST (*(volatile unsigned long *)(APB0_SD + 0x30))
  389. +#define CMD_XFER_START (1<<13)
  390. +#define CMD_XFER_END (0<<13)
  391. +#define RES_XFER_START (1<<12)
  392. +#define RES_XFER_END (0<<12)
  393. +#define RES_R1 (0<<9)
  394. +#define RES_R1b (1<<9)
  395. +#define RES_R2 (2<<9)
  396. +#define RES_R3 (3<<9)
  397. +#define RES_R6 (6<<9)
  398. +#define CMD_RES_ERROR (1<<8)
  399. +/* bits 0-5 cmd index */
  400. +
  401. +#define SD_CMDRES (*(volatile unsigned long *)(APB0_SD + 0x34))
  402. +#define STAT_CMD_XFER_START (1<<8)
  403. +#define STAT_RES_XFER_START (1<<7)
  404. +#define STAT_CMD_RES_ERR (1<<6)
  405. +#define STAT_CMD_RES_BUS_ERR (1<<5)
  406. +#define STAT_RES_TIMEOUT_ERR (1<<4)
  407. +#define STAT_RES_STARTBIT_ERR (1<<3)
  408. +#define STAT_RES_INDEX_ERR (1<<2)
  409. +#define STAT_RES_CRC_ERR (1<<1)
  410. +#define STAT_RES_ENDBIT_ERR (1<<0)
  411. +
  412. +#define SD_DATAT (*(volatile unsigned long *)(APB0_SD + 0x3C))
  413. +#define DATA_XFER_START (1<<13)
  414. +#define DATA_XFER_WRITE (1<<12)
  415. +#define DATA_XFER_READ (0<<12)
  416. +#define DATA_BUS_4LINES (1<<11) /* rk2705/6/8 does not support this mode */
  417. +#define DATA_BUS_1LINE (0<<11)
  418. +#define DATA_XFER_DMA_EN (1<<10)
  419. +#define DATA_XFER_DMA_DIS (0<<10)
  420. +#define DATA_XFER_MULTI (1<<9)
  421. +#define DATA_XFER_SINGLE (0<<9)
  422. +#define DATA_XFER_ERR (1<<8)
  423. +#define DATA_BUS_ERR (1<<7)
  424. +#define DATA_TIMEOUT_ERR (1<<6)
  425. +#define DATA_CRC_ERR (1<<5)
  426. +#define READ_DAT_STARTBIT_ERR (1<<4)
  427. +#define READ_DAT_ENDBIT_ERR (1<<3)
  428. +#define WRITE_DAT_NOERR (2<<0)
  429. +#define WRITE_DAT_CRC_ERR (5<<0)
  430. +#define WRITE_DAT_NO_RES (7<<0)
  431. +
  432. +#define SD_CMD (*(volatile unsigned long *)(APB0_SD + 0x40))
  433. +#define SD_RES3 (*(volatile unsigned long *)(APB0_SD + 0x44))
  434. +#define SD_RES2 (*(volatile unsigned long *)(APB0_SD + 0x48))
  435. +#define SD_RES1 (*(volatile unsigned long *)(APB0_SD + 0x4C))
  436. +#define SD_RES0 (*(volatile unsigned long *)(APB0_SD + 0x50))
  437. +
  438. +/* I2S controller */
  439. +#define APB0_I2S (ARM_BUS0_BASE + 0x00028000)
  440. +#define I2S_OPR (*(volatile unsigned long *)(APB0_I2S + 0x00))
  441. +#define I2S_TXR (*(volatile unsigned long *)(APB0_I2S + 0x04))
  442. +#define I2S_RXR (*(volatile unsigned long *)(APB0_I2S + 0x08))
  443. +#define I2S_TXCTL (*(volatile unsigned long *)(APB0_I2S + 0x0C))
  444. +#define I2S_RXCTL (*(volatile unsigned long *)(APB0_I2S + 0x10))
  445. +#define I2S_FIFOSTS (*(volatile unsigned long *)(APB0_I2S + 0x14))
  446. +#define I2S_IER (*(volatile unsigned long *)(APB0_I2S + 0x18))
  447. +#define I2S_ISR (*(volatile unsigned long *)(APB0_I2S + 0x1C))
  448. +
  449. +/* PWM timer */
  450. +#define APB0_PWM (ARM_BUS0_BASE + 0x0002C000)
  451. +#define PWMT0_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x00))
  452. +#define PWMT0_HRC (*(volatile unsigned long *)(APB0_PWM + 0x04))
  453. +#define PWMT0_LRC (*(volatile unsigned long *)(APB0_PWM + 0x08))
  454. +#define PWMT0_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x0C))
  455. +#define PWMT1_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x10))
  456. +#define PWMT1_HRC (*(volatile unsigned long *)(APB0_PWM + 0x14))
  457. +#define PWMT1_LRC (*(volatile unsigned long *)(APB0_PWM + 0x18))
  458. +#define PWMT1_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x1C))
  459. +#define PWMT2_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x20))
  460. +#define PWMT2_HRC (*(volatile unsigned long *)(APB0_PWM + 0x24))
  461. +#define PWMT2_LRC (*(volatile unsigned long *)(APB0_PWM + 0x28))
  462. +#define PWMT2_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x2C))
  463. +#define PWMT3_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x30))
  464. +#define PWMT3_HRC (*(volatile unsigned long *)(APB0_PWM + 0x34))
  465. +#define PWMT3_LRC (*(volatile unsigned long *)(APB0_PWM + 0x38))
  466. +#define PWMT3_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x3C))
  467. +
  468. +/* ADC converter */
  469. +#define APB0_ADC0 (ARM_BUS0_BASE + 0x00030000)
  470. +#define ADC_DATA (*(volatile unsigned long *)(APB0_ADC0 + 0x00))
  471. +#define ADC_STAT (*(volatile unsigned long *)(APB0_ADC0 + 0x04))
  472. +#define ADC_CTRL (*(volatile unsigned long *)(APB0_ADC0 + 0x08))
  473. +
  474. +/* 0x18034000 - 0x18038000 reserved */
  475. +
  476. +/* GPIO ports E,F */
  477. +#define APB0_GPIO1 (ARM_BUS0_BASE + 0x00038000)
  478. +#define GPIO_PEDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x00))
  479. +#define GPIO_PECON (*(volatile unsigned long *)(APB0_GPIO1 + 0x04))
  480. +#define GPIO_PFDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x08))
  481. +#define GPIO_PFCON (*(volatile unsigned long *)(APB0_GPIO1 + 0x0C))
  482. +
  483. +#define GPIO1_TEST (*(volatile unsigned long *)(APB0_GPIO1 + 0x20))
  484. +#define GPIO_IEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x24))
  485. +#define GPIO_IEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x28))
  486. +
  487. +#define GPIO_ISE (*(volatile unsigned long *)(APB0_GPIO1 + 0x34))
  488. +#define GPIO_ISF (*(volatile unsigned long *)(APB0_GPIO1 + 0x38))
  489. +
  490. +#define GPIO_IBEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x44))
  491. +#define GPIO_IBEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x48))
  492. +
  493. +#define GPIO_IEVE (*(volatile unsigned long *)(APB0_GPIO1 + 0x54))
  494. +#define GPIO_IEVF (*(volatile unsigned long *)(APB0_GPIO1 + 0x58))
  495. +
  496. +#define GPIO_ICE (*(volatile unsigned long *)(APB0_GPIO1 + 0x64))
  497. +#define GPIO_ICF (*(volatile unsigned long *)(APB0_GPIO1 + 0x68))
  498. +
  499. +#define GPIO1_ISR (*(volatile unsigned long *)(APB0_GPIO1 + 0x74))
  500. +
  501. +
  502. +/* 0x1803C000 - 0x18080000 reserved */
  503. +
  504. +/* Interrupt controller */
  505. +#define AHB0_INTC (ARM_BUS0_BASE + 0x00080000)
  506. +#define INTC_SCR0 (*(volatile unsigned long *)(AHB0_INTC + 0x00))
  507. +#define INTC_SCR1 (*(volatile unsigned long *)(AHB0_INTC + 0x04))
  508. +#define INTC_SCR2 (*(volatile unsigned long *)(AHB0_INTC + 0x08))
  509. +#define INTC_SCR3 (*(volatile unsigned long *)(AHB0_INTC + 0x0C))
  510. +#define INTC_SCR4 (*(volatile unsigned long *)(AHB0_INTC + 0x10))
  511. +#define INTC_SCR5 (*(volatile unsigned long *)(AHB0_INTC + 0x14))
  512. +#define INTC_SCR6 (*(volatile unsigned long *)(AHB0_INTC + 0x18))
  513. +#define INTC_SCR7 (*(volatile unsigned long *)(AHB0_INTC + 0x1C))
  514. +#define INTC_SCR8 (*(volatile unsigned long *)(AHB0_INTC + 0x20))
  515. +#define INTC_SCR9 (*(volatile unsigned long *)(AHB0_INTC + 0x24))
  516. +#define INTC_SCR10 (*(volatile unsigned long *)(AHB0_INTC + 0x28))
  517. +#define INTC_SCR11 (*(volatile unsigned long *)(AHB0_INTC + 0x2C))
  518. +#define INTC_SCR12 (*(volatile unsigned long *)(AHB0_INTC + 0x30))
  519. +#define INTC_SCR13 (*(volatile unsigned long *)(AHB0_INTC + 0x34))
  520. +#define INTC_SCR14 (*(volatile unsigned long *)(AHB0_INTC + 0x38))
  521. +#define INTC_SCR15 (*(volatile unsigned long *)(AHB0_INTC + 0x3C))
  522. +#define INTC_SCR16 (*(volatile unsigned long *)(AHB0_INTC + 0x40))
  523. +#define INTC_SCR17 (*(volatile unsigned long *)(AHB0_INTC + 0x44))
  524. +#define INTC_SCR18 (*(volatile unsigned long *)(AHB0_INTC + 0x48))
  525. +#define INTC_SCR19 (*(volatile unsigned long *)(AHB0_INTC + 0x4C))
  526. +#define INTC_SCR20 (*(volatile unsigned long *)(AHB0_INTC + 0x50))
  527. +#define INTC_SCR21 (*(volatile unsigned long *)(AHB0_INTC + 0x54))
  528. +#define INTC_SCR22 (*(volatile unsigned long *)(AHB0_INTC + 0x58))
  529. +#define INTC_SCR23 (*(volatile unsigned long *)(AHB0_INTC + 0x5C))
  530. +#define INTC_SCR24 (*(volatile unsigned long *)(AHB0_INTC + 0x60))
  531. +#define INTC_SCR25 (*(volatile unsigned long *)(AHB0_INTC + 0x64))
  532. +#define INTC_SCR26 (*(volatile unsigned long *)(AHB0_INTC + 0x68))
  533. +#define INTC_SCR27 (*(volatile unsigned long *)(AHB0_INTC + 0x6C))
  534. +#define INTC_SCR28 (*(volatile unsigned long *)(AHB0_INTC + 0x70))
  535. +#define INTC_SCR29 (*(volatile unsigned long *)(AHB0_INTC + 0x74))
  536. +#define INTC_SCR30 (*(volatile unsigned long *)(AHB0_INTC + 0x78))
  537. +#define INTC_SCR31 (*(volatile unsigned long *)(AHB0_INTC + 0x7C))
  538. +
  539. +#define INTC_ISR (*(volatile unsigned long *)(AHB0_INTC + 0x104))
  540. +#define INTC_IPR (*(volatile unsigned long *)(AHB0_INTC + 0x108))
  541. +#define INTC_IMR (*(volatile unsigned long *)(AHB0_INTC + 0x10C))
  542. +
  543. +#define INTC_IECR (*(volatile unsigned long *)(AHB0_INTC + 0x114))
  544. +#define INTC_ICCR (*(volatile unsigned long *)(AHB0_INTC + 0x118))
  545. +#define INTC_ISCR (*(volatile unsigned long *)(AHB0_INTC + 0x11C))
  546. +
  547. +#define IRQ_ARM_UART0 (1<<0)
  548. +#define IRQ_ARM_UART1 (1<<1)
  549. +#define IRQ_ARM_TIMER0 (1<<2)
  550. +#define IRQ_ARM_TIMER1 (1<<3)
  551. +#define IRQ_ARM_TIMER2 (1<<4)
  552. +#define IRQ_ARM_GPIO0 (1<<5)
  553. +#define IRQ_ARM_SW (1<<6)
  554. +#define IRQ_ARM_MAILBOX (1<<7)
  555. +#define IRQ_ARM_RTC (1<<8)
  556. +#define IRQ_ARM_SCU (1<<9)
  557. +#define IRQ_ARM_SD (1<<10)
  558. +#define IRQ_ARM_SPI (1<<11)
  559. +#define IRQ_ARM_HDMA (1<<12)
  560. +#define IRQ_ARM_A2A (1<<13)
  561. +#define IRQ_ARM_I2C (1<<14)
  562. +#define IRQ_ARM_I2S (1<<15)
  563. +#define IRQ_ARM_UDC (1<<16)
  564. +#define IRQ_ARM_UHC (1<<17)
  565. +#define IRQ_ARM_PWM0 (1<<18)
  566. +#define IRQ_ARM_PWM1 (1<<19)
  567. +#define IRQ_ARM_PWM2 (1<<20)
  568. +#define IRQ_ARM_PWM3 (1<<21)
  569. +#define IRQ_ARM_ADC (1<<22)
  570. +#define IRQ_ARM_GPIO1 (1<<23)
  571. +#define IRQ_ARM_VIP (1<<24)
  572. +#define IRQ_ARM_DWDMA (1<<25)
  573. +#define IRQ_ARM_NANDC (1<<26)
  574. +#define IRQ_ARM_LCDC (1<<27)
  575. +#define IRQ_ARM_DSP (1<<28)
  576. +#define IRQ_ARM_SW1 (1<<29)
  577. +#define IRQ_ARM_SW2 (1<<30)
  578. +#define IRQ_ARM_SW3 (1<<31)
  579. +
  580. +#define INTC_TEST (*(volatile unsigned long *)(AHB0_INTC + 0x124))
  581. +
  582. +/* Bus arbiter module */
  583. +#define AHB0_ARBITER (ARM_BUS0_BASE + 0x00084000)
  584. +#define ARB_MODE (*(volatile unsigned long *)(AHB0_ARBITER + 0x00))
  585. +#define ARB_PRIO1 (*(volatile unsigned long *)(AHB0_ARBITER + 0x04))
  586. +#define ARB_PRIO2 (*(volatile unsigned long *)(AHB0_ARBITER + 0x08))
  587. +#define ARB_PRIO3 (*(volatile unsigned long *)(AHB0_ARBITER + 0x0C))
  588. +#define ARB_PRIO4 (*(volatile unsigned long *)(AHB0_ARBITER + 0x10))
  589. +#define ARB_PRIO5 (*(volatile unsigned long *)(AHB0_ARBITER + 0x14))
  590. +#define ARB_PRIO6 (*(volatile unsigned long *)(AHB0_ARBITER + 0x18))
  591. +#define ARB_PRIO7 (*(volatile unsigned long *)(AHB0_ARBITER + 0x1C))
  592. +#define ARB_PRIO8 (*(volatile unsigned long *)(AHB0_ARBITER + 0x20))
  593. +#define ARB_PRIO9 (*(volatile unsigned long *)(AHB0_ARBITER + 0x24))
  594. +#define ARB_PRIO10 (*(volatile unsigned long *)(AHB0_ARBITER + 0x28))
  595. +#define ARB_PRIO11 (*(volatile unsigned long *)(AHB0_ARBITER + 0x2C))
  596. +#define ARB_PRIO12 (*(volatile unsigned long *)(AHB0_ARBITER + 0x30))
  597. +#define ARB_PRIO13 (*(volatile unsigned long *)(AHB0_ARBITER + 0x34))
  598. +#define ARB_PRIO14 (*(volatile unsigned long *)(AHB0_ARBITER + 0x38))
  599. +#define ARB_PRIO15 (*(volatile unsigned long *)(AHB0_ARBITER + 0x3C))
  600. +
  601. +/* Interprocessor communication module */
  602. +#define AHB0_CPU_MAILBOX (ARM_BUS0_BASE + 0x00088000)
  603. +#define MAILBOX_ID (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x00))
  604. +#define H2C_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x10))
  605. +#define H2C0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x20))
  606. +#define H2C0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
  607. +#define H2C1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x28))
  608. +#define H2C1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x2C))
  609. +#define H2C2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x30))
  610. +#define H2C2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
  611. +#define H2C3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x38))
  612. +#define H2C3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x3C))
  613. +
  614. +#define C2H_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x40))
  615. +#define C2H0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x50))
  616. +#define C2H0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x54))
  617. +#define C2H1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x58))
  618. +#define C2H1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x5C))
  619. +#define C2H2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x60))
  620. +#define C2H2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x64))
  621. +#define C2H3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x68))
  622. +#define C2H3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x6C))
  623. +
  624. +/* Debug module */
  625. +#define AHB0_CPU_DEBUGIF (ARM_BUS0_BASE + 0x0008C000)
  626. +
  627. +/* AHB DMA */
  628. +#define AHB0_HDMA (ARM_BUS0_BASE + 0x00090000)
  629. +#define HDMA_CON0 (*(volatile unsigned long *)(AHB0_HDMA + 0x00))
  630. +#define HDMA_CON1 (*(volatile unsigned long *)(AHB0_HDMA + 0x04))
  631. +#define HDMA_ISRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x08))
  632. +#define HDMA_IDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x0C))
  633. +#define HDMA_ICNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x10))
  634. +#define HDMA_ISRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x14))
  635. +#define HDMA_IDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x18))
  636. +#define HDMA_ICNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x1C))
  637. +#define HDMA_CSRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x20))
  638. +#define HDMA_CDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x24))
  639. +#define HDMA_CCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x28))
  640. +#define HDMA_CSRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x2C))
  641. +#define HDMA_CDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x30))
  642. +#define HDMA_CCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x34))
  643. +#define HDMA_ISR (*(volatile unsigned long *)(AHB0_HDMA + 0x38))
  644. +#define HDMA_DSR (*(volatile unsigned long *)(AHB0_HDMA + 0x3C))
  645. +#define HDMA_ISCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x40))
  646. +#define HDMA_IPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x44))
  647. +#define HDMA_IADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x48))
  648. +#define HDMA_ISCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x4C))
  649. +#define HDMA_IPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x50))
  650. +#define HDMA_IADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x54))
  651. +#define HDMA_CSCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x58))
  652. +#define HDMA_CPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x5C))
  653. +#define HDMA_CADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x60))
  654. +#define HDMA_CSCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x64))
  655. +#define HDMA_CPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x68))
  656. +#define HDMA_CADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x6C))
  657. +#define HDMA_PACNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x70))
  658. +#define HDMA_PACNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x74))
  659. +
  660. +/* AHB-to-AHB bridge controller */
  661. +#define AHB0_A2A_DMA (ARM_BUS0_BASE + 0x00094000)
  662. +#define A2A_CON0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x00))
  663. +#define A2A_ISRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x04))
  664. +#define A2A_IDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x08))
  665. +#define A2A_ICNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x0C))
  666. +#define A2A_CSRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x10))
  667. +#define A2A_CDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x14))
  668. +#define A2A_CCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x18))
  669. +#define A2A_CON1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x1C))
  670. +#define A2A_ISRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x20))
  671. +#define A2A_IDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x24))
  672. +#define A2A_ICNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x28))
  673. +#define A2A_CSRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x2C))
  674. +#define A2A_CDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x30))
  675. +#define A2A_CCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x34))
  676. +#define A2A_INT_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x38))
  677. +#define A2A_DMA_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x3C))
  678. +#define A2A_ERR_ADR0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x40))
  679. +#define A2A_ERR_OP0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x44))
  680. +#define A2A_ERR_ADR1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x48))
  681. +#define A2A_ERR_OP1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x4C))
  682. +#define A2A_LCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x50))
  683. +#define A2A_LCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x54))
  684. +#define A2A_DOMAIN (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x58))
  685. +
  686. +/* 0x18098000 - 0x180A000 reserved */
  687. +
  688. +/* USB device controller */
  689. +#define AHB0_UDC (ARM_BUS0_BASE + 0x000A0000)
  690. +#define PHY_TEST_EN (*(volatile unsigned long *)(AHB0_UDC + 0x00))
  691. +#define PHY_TEST (*(volatile unsigned long *)(AHB0_UDC + 0x04))
  692. +#define DEV_CTL (*(volatile unsigned long *)(AHB0_UDC + 0x08))
  693. +#define DEV_RMTWKP (1<<2)
  694. +#define DEV_SELF_PWR (1<<3)
  695. +#define DEV_SOFT_CN (1<<4)
  696. +#define DEV_RESUME (1<<5)
  697. +#define DEV_PHY16BIT (1<<6)
  698. +#define SOFT_POR (1<<7)
  699. +#define CSR_DONE (1<<8)
  700. +
  701. +#define DEV_INFO (*(volatile unsigned long *)(AHB0_UDC + 0x10))
  702. +#define DEV_EN (1<<7)
  703. +#define VBUS_STS (1<<20)
  704. +#define DEV_SPEED (3<<21)
  705. +
  706. +#define EN_INT (*(volatile unsigned long *)(AHB0_UDC + 0x14))
  707. +#define EN_SOF_INTR (1<<0)
  708. +#define EN_SETUP_INTR (1<<1)
  709. +#define EN_IN0_INTR (1<<2)
  710. +#define EN_OUT0_INTR (1<<3)
  711. +#define EN_USBRST_INTR (1<<4)
  712. +#define EN_RESUME_INTR (1<<5)
  713. +#define EN_SUSP_INTR (1<<6)
  714. +/* bit 7 reserved */
  715. +#define EN_BOUT1_INTR (1<<8)
  716. +#define EN_BIN2_INTR (1<<9)
  717. +#define EN_IIN3_INTR (1<<10)
  718. +#define EN_BOUT4_INTR (1<<11)
  719. +#define EN_BIN5_INTR (1<<12)
  720. +#define EN_IIN6_INTR (1<<13)
  721. +#define EN_BOUT7_INTR (1<<14)
  722. +#define EN_BIN8_INTR (1<<15)
  723. +#define EN_IIN9_INTR (1<<16)
  724. +#define EN_BOUT10_INTR (1<<17)
  725. +#define EN_BIN11_INTR (1<<18)
  726. +#define EN_IIN12_INTR (1<<19)
  727. +#define EN_BOUT13_INTR (1<<20)
  728. +#define EN_BIN14_INTR (1<<21)
  729. +#define EN_IIN15_INTR (1<<22)
  730. +/* bits 23-26 TEST */
  731. +/* bits 27-31 reserved */
  732. +
  733. +#define INT2FLAG (*(volatile unsigned long *)(AHB0_UDC + 0x18))
  734. +#define SOF_INTR (1<<0)
  735. +#define SETUP_INTR (1<<1)
  736. +#define IN0_INTR (1<<2)
  737. +#define OUT0_INTR (1<<3)
  738. +#define USBRST_INTR (1<<4)
  739. +#define RESUME_INTR (1<<5)
  740. +#define SUSP_INTR (1<<6)
  741. +#define CONN_INTR (1<<7) /* marked as reserved in DS */
  742. +#define BOUT1_INTR (1<<8)
  743. +#define BIN2_INTR (1<<9)
  744. +#define IIN3_INTR (1<<10)
  745. +#define BOUT4_INTR (1<<11)
  746. +#define BIN5_INTR (1<<12)
  747. +#define IIN6_INTR (1<<13)
  748. +#define BOUT7_INTR (1<<14)
  749. +#define BIN8_INTR (1<<15)
  750. +#define IIN9_INTR (1<<16)
  751. +#define BOUT10_INTR (1<<17)
  752. +#define BIN11_INTR (1<<18)
  753. +#define IIN12_INTR (1<<19)
  754. +#define BOUT13_INTR (1<<20)
  755. +#define BIN14_INTR (1<<21)
  756. +#define IIN15_INTR (1<<22)
  757. +/* bits 23-26 TEST */
  758. +/* bits 27-31 reserved */
  759. +
  760. +#define INTCON (*(volatile unsigned long *)(AHB0_UDC + 0x1C))
  761. +#define UDC_INTEN (1<<0)
  762. +#define UDC_INTEDGE_TRIG (1<<1)
  763. +#define UDC_INTHIGH_ACT (1<<2)
  764. +
  765. +#define SETUP1 (*(volatile unsigned long *)(AHB0_UDC + 0x20))
  766. +#define SETUP2 (*(volatile unsigned long *)(AHB0_UDC + 0x24))
  767. +#define AHBCON (*(volatile unsigned long *)(AHB0_UDC + 0x28))
  768. +#define RX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x30))
  769. +#define RX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x34))
  770. +#define RX0DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x38))
  771. +#define RX0DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x3C))
  772. +#define TX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x40))
  773. +#define TX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x44))
  774. +#define TX0BUF (*(volatile unsigned long *)(AHB0_UDC + 0x48))
  775. +#define TX0DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x4C))
  776. +#define TX0DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x50))
  777. +#define RX1STAT (*(volatile unsigned long *)(AHB0_UDC + 0x54))
  778. +#define RX1CON (*(volatile unsigned long *)(AHB0_UDC + 0x58))
  779. +#define RX1DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x5C))
  780. +#define RX1DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x60))
  781. +#define TX2STAT (*(volatile unsigned long *)(AHB0_UDC + 0x64))
  782. +#define TX2CON (*(volatile unsigned long *)(AHB0_UDC + 0x68))
  783. +#define TX2BUF (*(volatile unsigned long *)(AHB0_UDC + 0x6C))
  784. +#define TX2DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x70))
  785. +#define TX2DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x74))
  786. +#define TX3STAT (*(volatile unsigned long *)(AHB0_UDC + 0x78))
  787. +#define TX3CON (*(volatile unsigned long *)(AHB0_UDC + 0x7C))
  788. +#define TX3BUF (*(volatile unsigned long *)(AHB0_UDC + 0x80))
  789. +#define TX3DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x84))
  790. +#define TX3DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x88))
  791. +#define RX4STAT (*(volatile unsigned long *)(AHB0_UDC + 0x8C))
  792. +#define RX4CON (*(volatile unsigned long *)(AHB0_UDC + 0x90))
  793. +#define RX4DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x94))
  794. +#define RX4DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x98))
  795. +#define TX5STAT (*(volatile unsigned long *)(AHB0_UDC + 0x9C))
  796. +#define TX5CON (*(volatile unsigned long *)(AHB0_UDC + 0xA0))
  797. +#define TX5BUF (*(volatile unsigned long *)(AHB0_UDC + 0xA4))
  798. +#define TX5DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xA8))
  799. +#define TX5DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xAC))
  800. +#define TX6STAT (*(volatile unsigned long *)(AHB0_UDC + 0xB0))
  801. +#define TX6CON (*(volatile unsigned long *)(AHB0_UDC + 0xB4))
  802. +#define TX6BUF (*(volatile unsigned long *)(AHB0_UDC + 0xB8))
  803. +#define TX6DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xBC))
  804. +#define TX6DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xC0))
  805. +#define RX7STAT (*(volatile unsigned long *)(AHB0_UDC + 0xC4))
  806. +#define RX7CON (*(volatile unsigned long *)(AHB0_UDC + 0xC8))
  807. +#define RX7DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0xCC))
  808. +#define RX7DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0xD0))
  809. +#define TX8STAT (*(volatile unsigned long *)(AHB0_UDC + 0xD4))
  810. +#define TX8CON (*(volatile unsigned long *)(AHB0_UDC + 0xD8))
  811. +#define TX8BUF (*(volatile unsigned long *)(AHB0_UDC + 0xDC))
  812. +#define TX8DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xE0))
  813. +#define TX8DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xE4))
  814. +#define TX9STAT (*(volatile unsigned long *)(AHB0_UDC + 0xE8))
  815. +#define TX9CON (*(volatile unsigned long *)(AHB0_UDC + 0xEC))
  816. +#define TX9BUF (*(volatile unsigned long *)(AHB0_UDC + 0xF0))
  817. +#define TX9DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xF4))
  818. +#define TX9DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xF8))
  819. +#define RX10STAT (*(volatile unsigned long *)(AHB0_UDC + 0xFC))
  820. +#define RX10CON (*(volatile unsigned long *)(AHB0_UDC + 0x100))
  821. +#define RX10DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x104))
  822. +#define RX10DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x108))
  823. +#define TX11STAT (*(volatile unsigned long *)(AHB0_UDC + 0x10C))
  824. +#define TX11CON (*(volatile unsigned long *)(AHB0_UDC + 0x110))
  825. +#define TX11BUF (*(volatile unsigned long *)(AHB0_UDC + 0x114))
  826. +#define TX11DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x118))
  827. +#define TX11DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x11C))
  828. +#define TX12STAT (*(volatile unsigned long *)(AHB0_UDC + 0x120))
  829. +#define TX12CON (*(volatile unsigned long *)(AHB0_UDC + 0x124))
  830. +#define TX12BUF (*(volatile unsigned long *)(AHB0_UDC + 0x128))
  831. +#define TX12DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x12C))
  832. +#define TX12DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x130))
  833. +#define RX13STAT (*(volatile unsigned long *)(AHB0_UDC + 0x134))
  834. +#define RX13CON (*(volatile unsigned long *)(AHB0_UDC + 0x138))
  835. +#define RX13DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x13C))
  836. +#define RX13DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x140))
  837. +#define TX14STAT (*(volatile unsigned long *)(AHB0_UDC + 0x144))
  838. +#define TX14CON (*(volatile unsigned long *)(AHB0_UDC + 0x148))
  839. +#define TX14BUF (*(volatile unsigned long *)(AHB0_UDC + 0x14C))
  840. +#define TX14DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x150))
  841. +#define TX14DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x154))
  842. +#define TX15STAT (*(volatile unsigned long *)(AHB0_UDC + 0x158))
  843. +#define TX15CON (*(volatile unsigned long *)(AHB0_UDC + 0x15C))
  844. +#define TX15BUF (*(volatile unsigned long *)(AHB0_UDC + 0x160))
  845. +#define TX15DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x164))
  846. +#define TX15DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x168))
  847. +
  848. +/* RXnSTAT bits */
  849. +/* bits 10:0 RXLEN */
  850. +/* bits 15:11 reserved */
  851. +#define RXVOID (1<<16)
  852. +#define RXERR (1<<17)
  853. +#define RXACK (1<<18)
  854. +#define RXCFINT (1<<19) /* reserved for EP0 */
  855. +/* bits 23:20 reserved */
  856. +#define RXFULL (1<<24)
  857. +#define RXOVF (1<<25)
  858. +/* bits 31:26 reserved */
  859. +
  860. +/* RXnCON bits */
  861. +#define RXFFRC (1<<0)
  862. +#define RXCLR (1<<1)
  863. +#define RXSTALL (1<<2)
  864. +#define RXNAK (1<<3)
  865. +#define RXEPEN (1<<4)
  866. +#define RXVOIDINTEN (1<<5)
  867. +#define RXERRINTEN (1<<6)
  868. +#define RXACKINTEN (1<<7)
  869. +/* bits 31:8 reserved for EP0 */
  870. +/* bits 31:14 reserved for others */
  871. +
  872. +/* TxnSTAT */
  873. +/* bits 10:0 TXLEN */
  874. +/* bits 15:11 reserved */
  875. +#define TXVOID (1<<16)
  876. +#define TXERR (1<<17)
  877. +#define TXACK (1<<18)
  878. +#define TXDMADN (1<<19) /* reserved for EP0 */
  879. +#define TXCFINT (1<<20) /* reserved for EP0 */
  880. +/* bits 31:21 reserved */
  881. +
  882. +/* TXnCON bits */
  883. +#define TXCLR (1<<0)
  884. +#define TXSTALL (1<<1)
  885. +#define TXNAK (1<<2)
  886. +#define TXEPEN (1<<3) /* reserved for EP0 */
  887. +#define TXVOIDINTEN (1<<4)
  888. +#define TXERRINTEN (1<<5)
  889. +#define TXACKINTEN (1<<6)
  890. +#define TXDMADNEN (1<<7) /* reserved for EP0 */
  891. +/* bits 31:8 reserved */
  892. +
  893. +/* TXnBUF bits */
  894. +#define TXFULL (1<<0)
  895. +#define TXURF (1<<1)
  896. +#define TXDS0 (1<<2) /* reserved for EP0 */
  897. +#define TXDS1 (1<<3) /* reserved for EP0 */
  898. +/* bits 31:4 reserved */
  899. +
  900. +/* DMA bits */
  901. +#define DMA_START (1<<0)
  902. +/* bits 31:1 reserved */
  903. +
  904. +/* USB host controller */
  905. +#define AHB0_UHC (ARM_BUS0_BASE + 0x000A4000)
  906. +/* documentation missing */
  907. +
  908. +/* 0x180A8000 - 0x180B0000 reserved */
  909. +
  910. +/* Static/SDRAM memory controller */
  911. +#define AHB0_SDRSTMC (ARM_BUS0_BASE + 0x000B0000)
  912. +#define MCSDR_MODE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x100))
  913. +#define MCSDR_ADDMAP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x104))
  914. +#define MCSDR_ADDCFG (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x108))
  915. +#define MCSDR_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x10C))
  916. +#define MCSDR_T_REF (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x110))
  917. +#define MCSDR_T_RFC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x114))
  918. +#define MCSDR_T_MRD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x118))
  919. +#define MCSDR_T_RP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x120))
  920. +#define MCSDR_T_RCD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x124))
  921. +
  922. +#define MCST0_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x200))
  923. +#define MCST0_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x204))
  924. +#define MCST0_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x208))
  925. +#define MCST0_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x20C))
  926. +#define MCST0_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x210))
  927. +#define MCST0_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x214))
  928. +#define MCST0_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x218))
  929. +#define MCST0_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x21C))
  930. +#define MCST0_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x220))
  931. +
  932. +#define MCST1_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x300))
  933. +#define MCST1_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x304))
  934. +#define MCST1_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x308))
  935. +#define MCST1_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x30C))
  936. +#define MCST1_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x310))
  937. +#define MCST1_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x314))
  938. +#define MCST1_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x318))
  939. +#define MCST1_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x31C))
  940. +#define MCST1_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x320))
  941. +
  942. +/* 0x180B4000 - 0x180C000 reserved */
  943. +
  944. +/* VIP - video input processor */
  945. +#define AHB0_VIP (ARM_BUS0_BASE + 0x000C0000)
  946. +
  947. +/* 0x180C4000 - 0x180E8000 reserved */
  948. +
  949. +/* NAND flash controller */
  950. +#define AHB0_NANDC (ARM_BUS0_BASE + 0x000E8000)
  951. +
  952. +#define FMCTL (*(volatile unsigned long *)(AHB0_NANDC))
  953. +#define FM_RDY (1<<5) /* status of line R/B# */
  954. +#define FM_PROTECT (1<<4) /* WP# line (active low) */
  955. +/* bits 0-3 are chip selects */
  956. +
  957. +#define FMWAIT (*(volatile unsigned long *)(AHB0_NANDC + 0x04))
  958. +#define FLCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x08))
  959. +#define FL_RDY (1<<12)
  960. +#define FL_COR_EN (1<<11)
  961. +#define FL_INT_EN (1<<10)
  962. +#define FL_XFER_EN (1<<9)
  963. +#define FL_INTCLR_EN (1<<8)
  964. +/* bits 3-7 unknown */
  965. +#define FL_START (1<<2)
  966. +#define FL_WR (1<<1)
  967. +#define FL_RST (1<<0)
  968. +
  969. +#define BCHCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x0C))
  970. +/* bit 13 is used but unknown */
  971. +/* bit 12 is used but unknown */
  972. +#define BCH_WR (1<<1)
  973. +#define BCH_RST (1<<0)
  974. +
  975. +#define BCHST (*(volatile unsigned long *)(AHB0_NANDC + 0xD0))
  976. +/* bit 2 ERR ?? */
  977. +/* bit 0 ?? */
  978. +
  979. +#define FLASH_DATA(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x200 + (n<<9)))
  980. +#define FLASH_ADDR(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x204 + (n<<9)))
  981. +#define FLASH_CMD(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x208 + (n<<9)))
  982. +
  983. +#define PAGE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0xA00))
  984. +#define SPARE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0x1200))
  985. +
  986. +#define AHB0_ROM (ARM_BUS0_BASE + 0x000EC000)
  987. +#define AHB0_ES3 (ARM_BUS0_BASE + 0x000F4000)
  988. +#define AHB0_ES4 (ARM_BUS0_BASE + 0x000F8000)
  989. +#define AHB0_ES5 (ARM_BUS0_BASE + 0x000FC000)
  990. +#define AHB0_ES6 (ARM_BUS0_BASE + 0x00100000)
  991. +#define AHB0_EMD_SRAM (ARM_BUS0_BASE + 0x00200000)
  992. +
  993. +/* 0x18204000 - 0x1840000 reserved */
  994. +
  995. +/* 0x18400000 - 0x18484000 reserved*/
  996. +
  997. +#define AHB1_ARBITER 0x18484000
  998. +/* 0x18488000 - 0x186E8000 reserved*/
  999. +
  1000. +/* LCD controller */
  1001. +#define AHB1_LCDC 0x186E8000
  1002. +#define LCDC_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x00))
  1003. +/* bits 14-31 reserved */
  1004. +#define ALPHA24B (1<<13)
  1005. +#define UVBUFEXCH (1<<12)
  1006. +#define ALPHA(x) (((x)&0x07)<<9)
  1007. +#define Y_MIX (1<<8)
  1008. +#define LCDC_MCU (1<<7)
  1009. +#define RGB24B (1<<6)
  1010. +#define START_EVEN (1<<5)
  1011. +#define EVEN_EN (1<<4)
  1012. +#define RGB_DUMMY(x) (((x)&0x03)<<2)
  1013. +#define LCDC_EN (1<<1)
  1014. +#define LCDC_STOP (1<<0)
  1015. +#define MCU_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x04))
  1016. +
  1017. +#define ALPHA_BASE(x) (((x)&0x3f)<<8)
  1018. +#define MCU_CTRL_FIFO_EN (1<<6)
  1019. +#define MCU_CTRL_RS_HIGH (1<<5)
  1020. +#define MCU_CTRL_BUFF_WRITE (1<<2)
  1021. +#define MCU_CTRL_BUFF_START (1<<1)
  1022. +#define MCU_CTRL_BYPASS (1<<0)
  1023. +
  1024. +#define HOR_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x08))
  1025. +#define VERT_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x0C))
  1026. +#define HOR_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x10))
  1027. +#define VERT_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x14))
  1028. +#define HOR_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x18))
  1029. +#define VERT_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x1C))
  1030. +#define HOR_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x20))
  1031. +#define VERT_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x24))
  1032. +#define LINE0_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x28))
  1033. +#define LINE_ALPHA_EN (1<<14)
  1034. +#define LINE_SCALE_EN (1<<13)
  1035. +#define LINE_GBR (1<<12)
  1036. +#define LINE_RGB (0<<12)
  1037. +#define LINE_YUV_SRC (1<<11)
  1038. +#define LINE_RGB_SRC (0<<11)
  1039. +/* bits 0-10 Y_BASE */
  1040. +
  1041. +#define LINE0_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x2C))
  1042. +#define LINE1_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x30))
  1043. +#define LINE1_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x34))
  1044. +#define LINE2_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x38))
  1045. +#define LINE2_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x3C))
  1046. +#define LINE3_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x40))
  1047. +#define LINE3_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x44))
  1048. +#define START_X (*(volatile unsigned long *)(AHB1_LCDC + 0x48))
  1049. +#define START_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x4C))
  1050. +#define DELTA_X (*(volatile unsigned long *)(AHB1_LCDC + 0x50))
  1051. +#define DELTA_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x54))
  1052. +#define LCDC_INTR_MASK (*(volatile unsigned long *)(AHB1_LCDC + 0x58))
  1053. +#define INTR_MASK_LINE (1<<3)
  1054. +#define INTR_MASK_EVENLINE (0<<3)
  1055. +#define INTR_MASK_BUFF (1<<2)
  1056. +#define INTR_MASK_VERT (1<<1)
  1057. +#define INTR_MASK_HOR (1<<0)
  1058. +
  1059. +#define ALPHA_ALX (*(volatile unsigned long *)(AHB1_LCDC + 0x5C))
  1060. +#define ALPHA_ATY (*(volatile unsigned long *)(AHB1_LCDC + 0x60))
  1061. +#define ALPHA_ARX (*(volatile unsigned long *)(AHB1_LCDC + 0x64))
  1062. +#define ALPHA_ABY (*(volatile unsigned long *)(AHB1_LCDC + 0x68))
  1063. +
  1064. +#define ALPHA_BLX (*(volatile unsigned long *)(AHB1_LCDC + 0x6C))
  1065. +#define ALPHA_BTY (*(volatile unsigned long *)(AHB1_LCDC + 0x70))
  1066. +#define ALPHA_BRX (*(volatile unsigned long *)(AHB1_LCDC + 0x74))
  1067. +#define ALPHA_BBY (*(volatile unsigned long *)(AHB1_LCDC + 0x78))
  1068. +
  1069. +#define LCDC_STA (*(volatile unsigned long *)(AHB1_LCDC + 0x7C))
  1070. +#define LCDC_MCU_IDLE (1<<12)
  1071. +
  1072. +#define LCD_COMMAND (*(volatile unsigned long *)(AHB1_LCDC + 0x1000))
  1073. +#define LCD_DATA (*(volatile unsigned long *)(AHB1_LCDC + 0x1004))
  1074. +
  1075. +#define LCD_BUFF ((volatile void *)(AHB1_LCDC + 0x2000))
  1076. +/* High speed ADC interface */
  1077. +#define AHB1_HS_ADC 0x186EC000
  1078. +#define HSADC_DATA (*(volatile unsigned long *)(AHB1_HS_ADC + 0x00))
  1079. +#define HSADC_CTRL (*(volatile unsigned long *)(AHB1_HS_ADC + 0x04))
  1080. +#define HSADC_IER (*(volatile unsigned long *)(AHB1_HS_ADC + 0x08))
  1081. +#define HSADC_ISR (*(volatile unsigned long *)(AHB1_HS_ADC + 0x0C))
  1082. +
  1083. +/* AHB-to-AHB DMA controller */
  1084. +#define AHB1_DWDMA 0x186F0000
  1085. +#define DWDMA_SAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x00 + 0x58*n))
  1086. +#define DWDMA_DAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x08 + 0x58*n))
  1087. +#define DWDMA_LLP(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x10 + 0x58*n))
  1088. +#define DWDMA_CTL_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x18 + 0x58*n))
  1089. +#define CTLL_LLP_SRC_EN (1<<28)
  1090. +#define CTLL_LLP_DST_EN (1<<27)
  1091. +#define CTLL_SMS_M2 (1<<25)
  1092. +#define CTLL_SMS_M1 (0<<25)
  1093. +#define CTLL_DMS_M2 (1<<23)
  1094. +#define CTLL_DMS_M1 (0<<23)
  1095. +#define CTLL_FC_PER2PER (3<<20)
  1096. +#define CTLL_FC_PER2MEM (2<<20)
  1097. +#define CTLL_FC_MEM2PER (1<<20)
  1098. +#define CTLL_FC_MEM2MEM (0<<20)
  1099. +/* bit 19 reserved */
  1100. +#define CTLL_DST_SCATTER_EN (1<<18)
  1101. +#define CTLL_SRC_GATHER_EN (1<<17)
  1102. +#define CTLL_SRC_MSIZE_32 (4<<14)
  1103. +#define CTLL_SRC_MSIZE_16 (3<<14)
  1104. +#define CTLL_SRC_MSIZE_8 (2<<14)
  1105. +#define CTLL_SRC_MSIZE_4 (1<<14)
  1106. +#define CTLL_SRC_MSIZE_1 (0<<14)
  1107. +#define CTLL_DST_MSIZE_32 (4<<11)
  1108. +#define CTLL_DST_MSIZE_16 (3<<11)
  1109. +#define CTLL_DST_MSIZE_8 (2<<11)
  1110. +#define CTLL_DST_MSIZE_4 (1<<11)
  1111. +#define CTLL_DST_MSIZE_1 (0<<11)
  1112. +#define CTLL_SINC_NO (2<<9)
  1113. +#define CTLL_SINC_DEC (1<<9)
  1114. +#define CTLL_SINC_INC (0<<9)
  1115. +#define CTLL_DINC_NO (2<<7)
  1116. +#define CTLL_DINC_DEC (1<<7)
  1117. +#define CTLL_DINC_INC (0<<7)
  1118. +#define CTLL_SRC_TR_WIDTH_32 (2<<4)
  1119. +#define CTLL_SRC_TR_WIDTH_16 (1<<4)
  1120. +#define CTLL_SRC_TR_WIDTH_8 (0<<4)
  1121. +#define CTLL_DST_TR_WIDTH_32 (2<<1)
  1122. +#define CTLL_DST_TR_WIDTH_16 (1<<1)
  1123. +#define CTLL_DST_TR_WIDTH_8 (0<<1)
  1124. +#define CTLL_INT_EN (1<<0)
  1125. +
  1126. +#define DWDMA_CTL_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x1C + 0x58*n))
  1127. +#define DWDMA_SSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x20 + 0x58*n))
  1128. +#define DWDMA_DSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x28 + 0x58*n))
  1129. +#define DWDMA_SSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x30 + 0x58*n))
  1130. +#define DWDMA_DSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x38 + 0x58*n))
  1131. +#define DWDMA_CFG_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x40 + 0x58*n))
  1132. +#define CFGL_RELOAD_DST (1<<31)
  1133. +#define CFGL_RELOAD_SRC (1<<30)
  1134. +#define CFGL_MAX_ABRST(n) ((n)<<20)
  1135. +#define CFGL_SRC_HS_POL_LOW (1<<19)
  1136. +#define CFGL_DST_HS_POL_LOW (1<<18)
  1137. +#define CFGL_LOCK_B (1<<17)
  1138. +#define CFGL_LOCK_CH (1<<16)
  1139. +#define CFGL_LOCK_B_L(n) (((n)&0x03)<<14)
  1140. +#define CFGL_LOCK_CH_L(n) (((n)&0x03)<<12)
  1141. +#define CFGL_HS_SEL_SRC (1<<11)
  1142. +#define CFGL_HS_SEL_DST (1<<10)
  1143. +#define CFGL_FIFO_EMPTY (1<<9)
  1144. +#define CFGL_CH_SUSP (1<<8)
  1145. +#define CFGL_CH_PRIOR(n) (((n) & 0x03)<<5)
  1146. +/* bits 0-4 reserved */
  1147. +#define DWDMA_CFG_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x44 + 0x58*n))
  1148. +#define CFGH_DST_PER(n) (((n)&0x0F)<<11)
  1149. +#define CFGH_SRC_PER(n) (((n)&0x0F)<<7)
  1150. +#define CFGH_SRC_UPD_EN (1<<6)
  1151. +#define CFGH_DST_UPD_EN (1<<5)
  1152. +#define CFGH_PROTCTL(n) (((n)&0x07)<<2)
  1153. +#define CFGH_FIFO_MODE (1<<1)
  1154. +#define CFGH_FC_MODE (1<<0)
  1155. +
  1156. +#define DWDMA_SGR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x48 + 0x58*n))
  1157. +#define DWDMA_DSR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x50 + 0x58*n))
  1158. +
  1159. +#define DWDMA_RAW_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C0))
  1160. +#define DWDMA_RAW_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C8))
  1161. +#define DWDMA_RAW_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D0))
  1162. +#define DWDMA_RAW_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D8))
  1163. +#define DWDMA_RAW_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E0))
  1164. +
  1165. +#define DWDMA_STATUS_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E8))
  1166. +#define DWDMA_STATUS_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F0))
  1167. +#define DWDMA_STATUS_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F8))
  1168. +#define DWDMA_STATUS_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x300))
  1169. +#define DWDMA_STATUS_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x308))
  1170. +
  1171. +#define DWDMA_MASK_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x310))
  1172. +#define DWDMA_MASK_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x318))
  1173. +#define DWDMA_MASK_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x320))
  1174. +#define DWDMA_MASK_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x328))
  1175. +#define DWDMA_MASK_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x330))
  1176. +
  1177. +#define DWDMA_CLEAR_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x338))
  1178. +#define DWDMA_CLEAR_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x340))
  1179. +#define DWDMA_CLEAR_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x348))
  1180. +#define DWDMA_CLEAR_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x350))
  1181. +#define DWDMA_CLEAR_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x358))
  1182. +
  1183. +#define DWDMA_STATUS_INT (*(volatile unsigned long *)(AHB1_DWDMA + 0x360))
  1184. +
  1185. +#define DWDMA_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x368))
  1186. +#define DWDMA_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x370))
  1187. +#define DWDMA_S_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x378))
  1188. +#define DWDMA_S_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x380))
  1189. +#define DWDMA_L_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x388))
  1190. +#define DWDMA_L_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x390))
  1191. +
  1192. +#define DWDMA_DMA_CFG (*(volatile unsigned long *)(AHB1_DWDMA + 0x398))
  1193. +#define GLOB_EN (1<<0)
  1194. +#define DWDMA_DMA_CHEN (*(volatile unsigned long *)(AHB1_DWDMA + 0x3A0))
  1195. +#define DMACHEN_CH0 (0x101<<0)
  1196. +#define DMACHEN_CH1 (0x101<<1)
  1197. +#define DMACHEN_CH2 (0x101<<2)
  1198. +#define DMACHEN_CH3 (0x101<<3)
  1199. +
  1200. +/* ARM7 cache controller */
  1201. +#define ARM_CACHE_CTRL 0xEFFF0000
  1202. +#define DEVID (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x00))
  1203. +#define CACHEOP (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x04))
  1204. +#define CACHELKDN (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x08))
  1205. +
  1206. +#define MEMMAPA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x10))
  1207. +#define MEMMAPB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x14))
  1208. +#define MEMMAPC (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x18))
  1209. +#define MEMMAPD (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x1C))
  1210. +#define PFCNTRA_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x20))
  1211. +#define PFCNTRA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x24))
  1212. +#define PFCNTRB_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x28))
  1213. +#define PFCNTRB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x2C))
  1214. +
  1215. +/* Timer frequency */
  1216. +#define TIMER_FREQ 50000000
  1217. diff --git a/utils/hwstub/stub/rk27xx/target-config.h b/utils/hwstub/stub/rk27xx/target-config.h
  1218. new file mode 100644
  1219. index 0000000..6af214e
  1220. --- /dev/null
  1221. +++ b/utils/hwstub/stub/rk27xx/target-config.h
  1222. @@ -0,0 +1,9 @@
  1223. +#define CONFIG_RK27XX
  1224. +#define IRAM_ORIG 0x60000000
  1225. +#define IRAM_SIZE 0x8000
  1226. +#define DRAM_ORIG 0x60000000
  1227. +#define DRAM_SIZE (MEMORYSIZE * 0x100000)
  1228. +#define CPU_ARM
  1229. +#define ARM_ARCH 5
  1230. +#define USB_BASE 0x180A000
  1231. +#define USB_NUM_ENDPOINTS 2
  1232. diff --git a/utils/hwstub/stub/rk27xx/target.c b/utils/hwstub/stub/rk27xx/target.c
  1233. new file mode 100644
  1234. index 0000000..7f378d5
  1235. --- /dev/null
  1236. +++ b/utils/hwstub/stub/rk27xx/target.c
  1237. @@ -0,0 +1,206 @@
  1238. +/***************************************************************************
  1239. + * __________ __ ___.
  1240. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___
  1241. + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
  1242. + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
  1243. + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
  1244. + * \/ \/ \/ \/ \/
  1245. + * $Id$
  1246. + *
  1247. + * Copyright (C) 2013 by Marcin Bukat
  1248. + *
  1249. + * This program is free software; you can redistribute it and/or
  1250. + * modify it under the terms of the GNU General Public License
  1251. + * as published by the Free Software Foundation; either version 2
  1252. + * of the License, or (at your option) any later version.
  1253. + *
  1254. + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  1255. + * KIND, either express or implied.
  1256. + *
  1257. + ****************************************************************************/
  1258. +#include "stddef.h"
  1259. +#include "target.h"
  1260. +#include "system.h"
  1261. +#include "logf.h"
  1262. +#include "rk27xx.h"
  1263. +
  1264. +/**
  1265. + *
  1266. + * Global
  1267. + *
  1268. + */
  1269. +
  1270. +enum rk27xx_family_t
  1271. +{
  1272. + UNKNOWN,
  1273. + REV_A,
  1274. + REV_B,
  1275. +};
  1276. +
  1277. +static enum rk27xx_family_t g_rk27xx_family = UNKNOWN;
  1278. +static int g_atexit = HWSTUB_ATEXIT_OFF;
  1279. +
  1280. +static void power_off(void)
  1281. +{
  1282. + GPIO_PCCON &= ~(1<<0);
  1283. + while(1);
  1284. +}
  1285. +
  1286. +static void rk27xx_reset(void)
  1287. +{
  1288. + /* use Watchdog to reset */
  1289. + SCU_CLKCFG &= ~CLKCFG_WDT;
  1290. + WDTLR = 1;
  1291. + WDTCON = (1<<4) | (1<<3);
  1292. +
  1293. + /* Wait for reboot to kick in */
  1294. + while(1);
  1295. +}
  1296. +
  1297. +#define HZ 1000000
  1298. +
  1299. +static void backlight_init(void)
  1300. +{
  1301. + /* configure PD4 as output */
  1302. + GPIO_PDCON |= (1<<4);
  1303. +
  1304. + /* set PD4 low (backlight off) */
  1305. + GPIO_PDDR &= ~(1<<4);
  1306. +
  1307. + /* IOMUXB - set PWM0 pin as GPIO */
  1308. + SCU_IOMUXB_CON &= ~(1 << 11); /* type<<11<<channel */
  1309. +
  1310. + /* DIV/2, PWM reset */
  1311. + PWMT0_CTRL = (0<<9) | (1<<7);
  1312. +
  1313. + /* set pwm frequency */
  1314. + /* (apb_freq/pwm_freq)/pwm_div = (50 000 000/pwm_freq)/2 */
  1315. + PWMT0_LRC = 50000;
  1316. + PWMT0_HRC = 50000;
  1317. +
  1318. + /* reset counter */
  1319. + PWMT0_CNTR = 0x00;
  1320. +
  1321. + /* DIV/2, PWM output enable, PWM timer enable */
  1322. + PWMT0_CTRL = (0<<9) | (1<<3) | (1<<0);
  1323. +}
  1324. +
  1325. +void backlight_on(void)
  1326. +{
  1327. + /* enable PWM clock */
  1328. + SCU_CLKCFG &= ~CLKCFG_PWM;
  1329. +
  1330. + /* set output pin as PWM pin */
  1331. + SCU_IOMUXB_CON |= (1<<11); /* type<<11<<channel */
  1332. +
  1333. + /* pwm enable */
  1334. + PWMT0_CTRL |= (1<<3) | (1<<0);
  1335. +}
  1336. +
  1337. +void backlight_off(void)
  1338. +{
  1339. + /* setup PWM0 pin as GPIO which is pulled low */
  1340. + SCU_IOMUXB_CON &= ~(1<<11);
  1341. +
  1342. + /* stop pwm timer */
  1343. + PWMT0_CTRL &= ~(1<<3) | (1<<0);
  1344. +
  1345. + /* disable PWM clock */
  1346. + SCU_CLKCFG |= CLKCFG_PWM;
  1347. +}
  1348. +
  1349. +void target_init(void)
  1350. +{
  1351. + /* ungate all clocks */
  1352. + SCU_CLKCFG = 0;
  1353. +
  1354. + /* keep act line */
  1355. + GPIO_PCDR |= (1<<0);
  1356. + GPIO_PCCON |= (1<<0);
  1357. +
  1358. + /* disable watchdog */
  1359. + WDTCON &= ~(1<<3);
  1360. +
  1361. + /* ARM slow mode, HCLK:PCLK = 2:1 */
  1362. + SCU_DIVCON1 = ((SCU_DIVCON1 & ~0x1f) | 9);
  1363. + SCU_PLLCON1 = 0x1850310;
  1364. +
  1365. + /* wait for PLL lock */
  1366. + while (!(SCU_STATUS & 1))
  1367. + ;
  1368. +
  1369. + /* leave slow mode */
  1370. + SCU_DIVCON1 &= ~1;
  1371. +
  1372. + /* disable cache */
  1373. + DEVID = 0;
  1374. +
  1375. + backlight_init();
  1376. + backlight_on();
  1377. +
  1378. + /* detect revision */
  1379. + uint32_t rk27xx_id = SCU_ID;
  1380. + if(rk27xx_id == 0xa1000604)
  1381. + {
  1382. + logf("identified rk27xx REV_A \n");
  1383. + g_rk27xx_family = REV_A;
  1384. + }
  1385. + else if(rk27xx_id == 0xa10002b7)
  1386. + {
  1387. + logf("identified rk27xx REV_B \n");
  1388. + g_rk27xx_family = REV_B;
  1389. + }
  1390. + else
  1391. + {
  1392. + logf("unknown rk27xx revision \n");
  1393. + }
  1394. +}
  1395. +
  1396. +static struct usb_resp_info_target_t g_target =
  1397. +{
  1398. + .id = HWSTUB_TARGET_RK27,
  1399. + .name = "Rockchip RK27XX"
  1400. +};
  1401. +
  1402. +int target_get_info(int info, void **buffer)
  1403. +{
  1404. +#if 0
  1405. + if(info == HWSTUB_INFO_STMP)
  1406. + {
  1407. + g_stmp.chipid = __XTRACT(HW_DIGCTL_CHIPID, PRODUCT_CODE);
  1408. + g_stmp.rev = __XTRACT(HW_DIGCTL_CHIPID, REVISION);
  1409. + g_stmp.is_supported = g_stmp_family != 0;
  1410. + *buffer = &g_stmp;
  1411. + return sizeof(g_stmp);
  1412. + }
  1413. +#endif
  1414. + if(info == HWSTUB_INFO_TARGET)
  1415. + {
  1416. + *buffer = &g_target;
  1417. + return sizeof(g_target);
  1418. + }
  1419. + else
  1420. + return -1;
  1421. +}
  1422. +
  1423. +int target_atexit(int method)
  1424. +{
  1425. + g_atexit = method;
  1426. + return 0;
  1427. +}
  1428. +
  1429. +void target_exit(void)
  1430. +{
  1431. + switch(g_atexit)
  1432. + {
  1433. + case HWSTUB_ATEXIT_OFF:
  1434. + power_off();
  1435. + // fallthrough in case of return
  1436. + case HWSTUB_ATEXIT_REBOOT:
  1437. + rk27xx_reset();
  1438. + // fallthrough in case of return
  1439. + case HWSTUB_ATEXIT_NOP:
  1440. + default:
  1441. + return;
  1442. + }
  1443. +}
  1444. diff --git a/utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c b/utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c
  1445. new file mode 100644
  1446. index 0000000..1ab2a25
  1447. --- /dev/null
  1448. +++ b/utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c
  1449. @@ -0,0 +1,241 @@
  1450. +/***************************************************************************
  1451. + * __________ __ ___.
  1452. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___
  1453. + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
  1454. + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
  1455. + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
  1456. + * \/ \/ \/ \/ \/
  1457. + *
  1458. + *
  1459. + * Copyright (C) 2013 Marcin Bukat & Amaury Pauly
  1460. + *
  1461. + * This program is free software; you can redistribute it and/or
  1462. + * modify it under the terms of the GNU General Public License
  1463. + * as published by the Free Software Foundation; either version 2
  1464. + * of the License, or (at your option) any later version.
  1465. + *
  1466. + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  1467. + * KIND, either express or implied.
  1468. + *
  1469. + ****************************************************************************/
  1470. +#include "usb_drv.h"
  1471. +#include "config.h"
  1472. +#include "memory.h"
  1473. +#include "rk27xx.h"
  1474. +
  1475. +#define USB_FULL_SPEED 0
  1476. +#define USB_HIGH_SPEED 1
  1477. +#define CTL_MAX_SIZE 64
  1478. +
  1479. +/* usecs may be at most 2^32/200 (~21 seconds) for 200MHz max cpu freq */
  1480. +static void udelay(unsigned usecs)
  1481. +{
  1482. + unsigned cycles_per_usec;
  1483. + unsigned delay;
  1484. +
  1485. + cycles_per_usec = (200000000 + 999999) / 1000000;
  1486. +
  1487. + delay = (usecs * cycles_per_usec) / 5;
  1488. +
  1489. + asm volatile(
  1490. + "1: subs %0, %0, #1 \n" /* 1 cycle */
  1491. + " nop \n" /* 1 cycle */
  1492. + " bne 1b \n" /* 3 cycles */
  1493. + : : "r"(delay)
  1494. + );
  1495. +}
  1496. +
  1497. +/* OK */
  1498. +void usb_drv_set_address(int address)
  1499. +{
  1500. + (void)address;
  1501. + /* UDC sets this automaticaly */
  1502. +}
  1503. +
  1504. +/* endpoints */
  1505. +
  1506. +int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
  1507. +{
  1508. + (void)endpoint;
  1509. + (void)ptr;
  1510. + (void)length;
  1511. +
  1512. + return 0;
  1513. +}
  1514. +
  1515. +int usb_drv_send(int endpoint, void* ptr, int length)
  1516. +{
  1517. + (void)endpoint;
  1518. +
  1519. + int xfer_size;
  1520. + char *buf = (char *)ptr;
  1521. + int xfer_len = length;
  1522. +
  1523. + /* commit_discard_idcache(); */
  1524. +
  1525. + while (xfer_len >= 0)
  1526. + {
  1527. + while (TX0BUF & TXFULL)
  1528. + ;
  1529. +
  1530. + xfer_size = MIN(xfer_len, CTL_MAX_SIZE);
  1531. + TX0STAT = xfer_size; /* size of the transfer */
  1532. + TX0DMALM_IADDR = (uint32_t)buf; /* local buffer address */
  1533. + TX0DMAINCTL = DMA_START; /* start DMA */
  1534. + TX0CON &= ~TXNAK; /* clear NAK */
  1535. +
  1536. + while (!(INT2FLAG & IN0_INTR))
  1537. + ;
  1538. +
  1539. + xfer_len -= xfer_size;
  1540. + buf += xfer_size;
  1541. + }
  1542. +
  1543. + return 0;
  1544. +}
  1545. +
  1546. +int usb_drv_recv(int endpoint, void* ptr, int length)
  1547. +{
  1548. + (void)endpoint;
  1549. +
  1550. + char *buf = (char *)ptr;
  1551. + int xfer_len = length;
  1552. + int xfer_size;
  1553. +
  1554. + do
  1555. + {
  1556. + RX0CON &= ~RXNAK;
  1557. + RX0DMAOUTLMADDR = (uint32_t)buf; /* buffer address */
  1558. + RX0DMACTLO = DMA_START; /* start DMA */
  1559. +
  1560. + while (!(INT2FLAG & OUT0_INTR))
  1561. + ;
  1562. +
  1563. + /* get transaction size */
  1564. + xfer_size = RX0STAT & 0xffff;
  1565. +
  1566. + xfer_len -= xfer_size;
  1567. + buf += xfer_size;
  1568. + } while (xfer_len > 0);
  1569. +
  1570. + return 0;
  1571. +}
  1572. +
  1573. +int usb_drv_recv_nonblocking(int endpoint, void* ptr, int length)
  1574. +{
  1575. + (void)endpoint;
  1576. + (void)ptr;
  1577. + (void)length;
  1578. +
  1579. + return 0;
  1580. +}
  1581. +
  1582. +/* OK */
  1583. +int usb_drv_port_speed(void)
  1584. +{
  1585. + return ((DEV_INFO & DEV_SPEED) ? USB_FULL_SPEED : USB_HIGH_SPEED);
  1586. +}
  1587. +
  1588. +/* OK */
  1589. +void usb_drv_stall(int endpoint, bool stall, bool in)
  1590. +{
  1591. + /* ctrl only anyway */
  1592. + (void)endpoint;
  1593. +
  1594. + if(in)
  1595. + {
  1596. + if(stall)
  1597. + TX0CON |= TXSTALL;
  1598. + else
  1599. + TX0CON &= ~TXSTALL;
  1600. + }
  1601. + else
  1602. + {
  1603. + if (stall)
  1604. + RX0CON |= RXSTALL;
  1605. + else
  1606. + RX0CON &= ~RXSTALL; /* doc says Auto clear by UDC 2.0 */
  1607. + }
  1608. +}
  1609. +
  1610. +void usb_drv_configure_endpoint(int ep_num, int type)
  1611. +{
  1612. + /* todo */
  1613. + (void)ep_num;
  1614. + (void)type;
  1615. +}
  1616. +
  1617. +static void udc_phy_reset(void)
  1618. +{
  1619. + DEV_CTL |= SOFT_POR;
  1620. + udelay(10000); /* min 10ms */
  1621. + DEV_CTL &= ~SOFT_POR;
  1622. +}
  1623. +
  1624. +static void udc_soft_connect(void)
  1625. +{
  1626. + DEV_CTL |= CSR_DONE |
  1627. + DEV_SOFT_CN |
  1628. + DEV_SELF_PWR;
  1629. +}
  1630. +
  1631. +void usb_drv_init(void)
  1632. +{
  1633. + /* just to be sure the clock isnt gated */
  1634. + SCU_CLKCFG &= ~CLKCFG_UDC;
  1635. +
  1636. + udc_phy_reset();
  1637. + udelay(10000);
  1638. + udc_soft_connect();
  1639. +
  1640. + EN_INT = EN_SUSP_INTR | /* Enable Suspend Irq */
  1641. + EN_RESUME_INTR | /* Enable Resume Irq */
  1642. + EN_USBRST_INTR | /* Enable USB Reset Irq */
  1643. + EN_OUT0_INTR | /* Enable OUT Token receive Irq EP0 */
  1644. + EN_IN0_INTR | /* Enable IN Token transmit Irq EP0 */
  1645. + EN_SETUP_INTR; /* Enable SETUP Packet Receive Irq */
  1646. +
  1647. + INTCON = UDC_INTHIGH_ACT | /* interrupt high active */
  1648. + UDC_INTEN; /* enable EP0 irqs */
  1649. +
  1650. + TX0CON = TXACKINTEN | /* Set as one to enable the EP0 tx irq */
  1651. + TXNAK; /* Set as one to response NAK handshake */
  1652. +
  1653. + RX0CON = RXACKINTEN |
  1654. + RXEPEN | /* Endpoint 0 Enable. When cleared the
  1655. + * endpoint does not respond to an SETUP
  1656. + * or OUT token */
  1657. + RXNAK; /* Set as one to response NAK handshake */
  1658. +}
  1659. +
  1660. +void usb_drv_exit(void)
  1661. +{
  1662. + /* udc module reset */
  1663. + SCU_RSTCFG |= (1<<1);
  1664. + udelay(10);
  1665. + SCU_RSTCFG &= ~(1<<1);
  1666. +}
  1667. +
  1668. +int usb_drv_recv_setup(struct usb_ctrlrequest *req)
  1669. +{
  1670. + uint32_t setup_data[2];
  1671. +
  1672. +backlight_off();
  1673. +
  1674. + /* wait for setup */
  1675. + while(!(INT2FLAG & SETUP_INTR))
  1676. + ;
  1677. +
  1678. +backlight_on();
  1679. +
  1680. + /* copy setup data from packet */
  1681. + setup_data[0] = SETUP1;
  1682. + setup_data[1] = SETUP2;
  1683. +
  1684. + asm volatile("":::"memory");
  1685. +
  1686. + /* copy */
  1687. + memcpy(req, (void *)setup_data, sizeof(struct usb_ctrlrequest));
  1688. +
  1689. + return 0;
  1690. +}
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