entity source is
port(
        clk      : in   bit;
        day      : in   bit;
    vdd      : in   bit;
    vss      : in   bit;
    i        : in   bit_vector(3 downto 0);
    reset    : in   bit;
    door     : out  bit;
        alarm    : out  bit
     );
end entity source;
ARCHITECTURE fsm of source IS
TYPE state_type IS (E0, Ea, E1, E2, E3, E4, E5);
SIGNAL current_state, next_state: state_type;



--pragma CURRENT_STATE current_state
--pragma NEXT_STATE    next_state
--pragma CLOCK         clk


BEGIN
-- Process (1): Transition and Generation functions
CS: PROCESS (current_state, i, reset) IS
BEGIN
-- Next state Transition function = f(inputs)
if (reset = '1') THEN next_state <= E0;
else
case current_state is
WHEN E0 =>

IF (i="0010") THEN
next_state <= E1;
ELSIF  (i="1010" AND day='1') THEN

next_state <= E5;
Else
next_state <= Ea;
end if;


WHEN E1 =>

IF i="0110" THEN
next_state <= E2;
ELSIF  i="1010" AND day='1' THEN
next_state <= E5;
Else
next_state <= Ea;
end if;

WHEN E2 =>

IF i="1111" THEN
next_state <= E3;
ELSIF  i="1010" AND day='1' THEN

next_state <= E5;
Else
next_state <= Ea;
end if;
WHEN E3 =>

IF i="0000" THEN
next_state <= E4;
ELSIF  i="1010" AND day='1' THEN
next_state <= E5;
Else
next_state <= Ea;
END IF;

WHEN E4 =>

IF i="0101" THEN
next_state <= E5;
ELSIF  i="1010" AND day='1' THEN

next_state <= E5;
Else
next_state <= Ea;
end if;
WHEN E5 =>

next_state <= E5;

WHEN Ea =>

next_state <= Ea;



end case;
end if;
-- output generation function =f(states)
case current_state is

when E0 =>
        alarm <= '0';
            door  <= '0';
        when E1 =>
       alarm <= '0';
           door  <= '0';
        when E2 =>
        alarm <= '0';
            door  <= '0';
        when E3 =>
        alarm <= '0';
            door  <= '0';
        when E4 =>
            alarm <= '0';
            door  <= '0';
        when E5 =>
            alarm <= '0';
            door  <= '1';
        when Ea =>
            alarm <= '1';
            door  <= '0';
end case;
end process CS;
-- Process (2): State update (sequential)
Operation: PROCESS (clk)
BEGIN
 if (clk='1' and not clk'stable) then
      current_state <= next_state;
    end if;

END PROCESS Operation;
END ARCHITECTURE fsm;