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  1. /*
  2.  * ar8216.c: AR8216 switch driver
  3.  *
  4.  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  5.  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  6.  *
  7.  * This program is free software; you can redistribute it and/or
  8.  * modify it under the terms of the GNU General Public License
  9.  * as published by the Free Software Foundation; either version 2
  10.  * of the License, or (at your option) any later version.
  11.  *
  12.  * This program is distributed in the hope that it will be useful,
  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.  * GNU General Public License for more details.
  16.  */
  17.  
  18. #include <linux/if.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/list.h>
  22. #include <linux/if_ether.h>
  23. #include <linux/skbuff.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/netlink.h>
  26. #include <linux/bitops.h>
  27. #include <net/genetlink.h>
  28. #include <linux/switch.h>
  29. #include <linux/delay.h>
  30. #include <linux/phy.h>
  31. #include <linux/netdevice.h>
  32. #include <linux/etherdevice.h>
  33. #include <linux/lockdep.h>
  34. #include <linux/ar8216_platform.h>
  35. #include <linux/workqueue.h>
  36. #include <linux/of_device.h>
  37. #include <linux/leds.h>
  38. #include <linux/gpio.h>
  39.  
  40. #include "ar8216.h"
  41.  
  42. /* size of the vlan table */
  43. #define AR8X16_MAX_VLANS    128
  44. #define AR8X16_PROBE_RETRIES    10
  45. #define AR8X16_MAX_PORTS    8
  46.  
  47. #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  48.  
  49. struct ar8xxx_priv;
  50.  
  51. #define AR8XXX_CAP_GIGE         BIT(0)
  52. #define AR8XXX_CAP_MIB_COUNTERS     BIT(1)
  53.  
  54. enum {
  55.     AR8XXX_VER_AR8216 = 0x01,
  56.     AR8XXX_VER_AR8236 = 0x03,
  57.     AR8XXX_VER_AR8316 = 0x10,
  58.     AR8XXX_VER_AR8327 = 0x12,
  59.     AR8XXX_VER_AR8337 = 0x13,
  60. };
  61.  
  62. struct ar8xxx_mib_desc {
  63.     unsigned int size;
  64.     unsigned int offset;
  65.     const char *name;
  66. };
  67.  
  68. struct ar8xxx_chip {
  69.     unsigned long caps;
  70.  
  71.     int (*hw_init)(struct ar8xxx_priv *priv);
  72.     void (*cleanup)(struct ar8xxx_priv *priv);
  73.  
  74.     void (*init_globals)(struct ar8xxx_priv *priv);
  75.     void (*init_port)(struct ar8xxx_priv *priv, int port);
  76.     void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  77.     u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  78.     int (*atu_flush)(struct ar8xxx_priv *priv);
  79.     void (*vtu_flush)(struct ar8xxx_priv *priv);
  80.     void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vlan);
  81.  
  82.     const struct ar8xxx_mib_desc *mib_decs;
  83.     unsigned num_mibs;
  84. };
  85.  
  86. enum ar8327_led_pattern {
  87.     AR8327_LED_PATTERN_OFF = 0,
  88.     AR8327_LED_PATTERN_BLINK,
  89.     AR8327_LED_PATTERN_ON,
  90.     AR8327_LED_PATTERN_RULE,
  91. };
  92.  
  93. struct ar8327_led_entry {
  94.     unsigned reg;
  95.     unsigned shift;
  96. };
  97.  
  98. struct ar8327_led {
  99.     struct led_classdev cdev;
  100.     struct ar8xxx_priv *sw_priv;
  101.  
  102.     char *name;
  103.     bool active_low;
  104.     u8 led_num;
  105.     enum ar8327_led_mode mode;
  106.  
  107.     struct mutex mutex;
  108.     spinlock_t lock;
  109.     struct work_struct led_work;
  110.     bool enable_hw_mode;
  111.     enum ar8327_led_pattern pattern;
  112. };
  113.  
  114. struct ar8216_data {
  115.     u8 vlan_tagged;
  116. };
  117.  
  118. struct ar8327_data {
  119.     u8 vlan_tagged[AR8X16_MAX_VLANS];
  120.     u32 port0_status;
  121.     u32 port6_status;
  122.  
  123.     struct ar8327_led **leds;
  124.     unsigned int num_leds;
  125. };
  126.  
  127. struct ar8xxx_priv {
  128.     struct switch_dev dev;
  129.     struct mii_bus *mii_bus;
  130.     struct phy_device *phy;
  131.  
  132.     u32 (*read)(struct ar8xxx_priv *priv, int reg);
  133.     void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
  134.     u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
  135.  
  136.     int (*get_port_link)(unsigned port);
  137.  
  138.     const struct net_device_ops *ndo_old;
  139.     struct net_device_ops ndo;
  140.     struct mutex reg_mutex;
  141.     u8 chip_ver;
  142.     u8 chip_rev;
  143.     const struct ar8xxx_chip *chip;
  144.     union {
  145.         struct ar8216_data ar8216;
  146.         struct ar8327_data ar8327;
  147.     } chip_data;
  148.     bool initialized;
  149.     bool port4_phy;
  150.     char buf[2048];
  151.  
  152.     bool init;
  153.     bool mii_lo_first;
  154.  
  155.     struct mutex mib_lock;
  156.     struct delayed_work mib_work;
  157.     int mib_next_port;
  158.     u64 *mib_stats;
  159.  
  160.     struct list_head list;
  161.     unsigned int use_count;
  162.  
  163.     /* all fields below are cleared on reset */
  164.     bool vlan;
  165.     u16 vlan_id[AR8X16_MAX_VLANS];
  166.     u8 vlan_table[AR8X16_MAX_VLANS];
  167.     u16 pvid[AR8X16_MAX_PORTS];
  168.  
  169.     /* mirroring */
  170.     bool mirror_rx;
  171.     bool mirror_tx;
  172.     int source_port;
  173.     int monitor_port;
  174. };
  175.  
  176. #define MIB_DESC(_s , _o, _n)   \
  177.     {           \
  178.         .size = (_s),   \
  179.         .offset = (_o), \
  180.         .name = (_n),   \
  181.     }
  182.  
  183. static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  184.     MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  185.     MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  186.     MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  187.     MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  188.     MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  189.     MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  190.     MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  191.     MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  192.     MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  193.     MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  194.     MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  195.     MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  196.     MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  197.     MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  198.     MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  199.     MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  200.     MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  201.     MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  202.     MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  203.     MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  204.     MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  205.     MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  206.     MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  207.     MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  208.     MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  209.     MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  210.     MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  211.     MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  212.     MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  213.     MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  214.     MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  215.     MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  216.     MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  217.     MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  218.     MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  219.     MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  220.     MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  221. };
  222.  
  223. static const struct ar8xxx_mib_desc ar8236_mibs[] = {
  224.     MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  225.     MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  226.     MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  227.     MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  228.     MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  229.     MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  230.     MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
  231.     MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
  232.     MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
  233.     MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
  234.     MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
  235.     MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
  236.     MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
  237.     MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
  238.     MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
  239.     MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
  240.     MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
  241.     MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
  242.     MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
  243.     MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
  244.     MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
  245.     MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
  246.     MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
  247.     MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
  248.     MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
  249.     MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
  250.     MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
  251.     MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
  252.     MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
  253.     MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
  254.     MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
  255.     MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
  256.     MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
  257.     MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
  258.     MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
  259.     MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
  260.     MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
  261.     MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
  262.     MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
  263. };
  264.  
  265. static DEFINE_MUTEX(ar8xxx_dev_list_lock);
  266. static LIST_HEAD(ar8xxx_dev_list);
  267.  
  268. static inline struct ar8xxx_priv *
  269. swdev_to_ar8xxx(struct switch_dev *swdev)
  270. {
  271.     return container_of(swdev, struct ar8xxx_priv, dev);
  272. }
  273.  
  274. static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
  275. {
  276.     return priv->chip->caps & AR8XXX_CAP_GIGE;
  277. }
  278.  
  279. static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
  280. {
  281.     return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
  282. }
  283.  
  284. static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
  285. {
  286.     return priv->chip_ver == AR8XXX_VER_AR8216;
  287. }
  288.  
  289. static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
  290. {
  291.     return priv->chip_ver == AR8XXX_VER_AR8236;
  292. }
  293.  
  294. static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
  295. {
  296.     return priv->chip_ver == AR8XXX_VER_AR8316;
  297. }
  298.  
  299. static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
  300. {
  301.     return priv->chip_ver == AR8XXX_VER_AR8327;
  302. }
  303.  
  304. static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
  305. {
  306.     return priv->chip_ver == AR8XXX_VER_AR8337;
  307. }
  308.  
  309. static inline void
  310. split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  311. {
  312.     regaddr >>= 1;
  313.     *r1 = regaddr & 0x1e;
  314.  
  315.     regaddr >>= 5;
  316.     *r2 = regaddr & 0x7;
  317.  
  318.     regaddr >>= 3;
  319.     *page = regaddr & 0x1ff;
  320. }
  321.  
  322. static u32
  323. ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
  324. {
  325.     struct mii_bus *bus = priv->mii_bus;
  326.     u16 r1, r2, page;
  327.     u16 lo, hi;
  328.  
  329.     split_addr((u32) reg, &r1, &r2, &page);
  330.  
  331.     mutex_lock(&bus->mdio_lock);
  332.  
  333.     bus->write(bus, 0x18, 0, page);
  334.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  335.     lo = bus->read(bus, 0x10 | r2, r1);
  336.     hi = bus->read(bus, 0x10 | r2, r1 + 1);
  337.  
  338.     mutex_unlock(&bus->mdio_lock);
  339.  
  340.     return (hi << 16) | lo;
  341. }
  342.  
  343. static void
  344. ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
  345. {
  346.     struct mii_bus *bus = priv->mii_bus;
  347.     u16 r1, r2, r3;
  348.     u16 lo, hi;
  349.  
  350.     split_addr((u32) reg, &r1, &r2, &r3);
  351.     lo = val & 0xffff;
  352.     hi = (u16) (val >> 16);
  353.  
  354.     mutex_lock(&bus->mdio_lock);
  355.  
  356.     bus->write(bus, 0x18, 0, r3);
  357.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  358.     if (priv->mii_lo_first) {
  359.         bus->write(bus, 0x10 | r2, r1, lo);
  360.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  361.     } else {
  362.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  363.         bus->write(bus, 0x10 | r2, r1, lo);
  364.     }
  365.  
  366.     mutex_unlock(&bus->mdio_lock);
  367. }
  368.  
  369. static u32
  370. ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  371. {
  372.     struct mii_bus *bus = priv->mii_bus;
  373.     u16 r1, r2, page;
  374.     u16 lo, hi;
  375.     u32 ret;
  376.  
  377.     split_addr((u32) reg, &r1, &r2, &page);
  378.  
  379.     mutex_lock(&bus->mdio_lock);
  380.  
  381.     bus->write(bus, 0x18, 0, page);
  382.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  383.  
  384.     lo = bus->read(bus, 0x10 | r2, r1);
  385.     hi = bus->read(bus, 0x10 | r2, r1 + 1);
  386.  
  387.     ret = hi << 16 | lo;
  388.     ret &= ~mask;
  389.     ret |= val;
  390.  
  391.     lo = ret & 0xffff;
  392.     hi = (u16) (ret >> 16);
  393.  
  394.     if (priv->mii_lo_first) {
  395.         bus->write(bus, 0x10 | r2, r1, lo);
  396.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  397.     } else {
  398.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  399.         bus->write(bus, 0x10 | r2, r1, lo);
  400.     }
  401.  
  402.     mutex_unlock(&bus->mdio_lock);
  403.  
  404.     return ret;
  405. }
  406.  
  407.  
  408. static void
  409. ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
  410.              u16 dbg_addr, u16 dbg_data)
  411. {
  412.     struct mii_bus *bus = priv->mii_bus;
  413.  
  414.     mutex_lock(&bus->mdio_lock);
  415.     bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
  416.     bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
  417.     mutex_unlock(&bus->mdio_lock);
  418. }
  419.  
  420. static void
  421. ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
  422. {
  423.     struct mii_bus *bus = priv->mii_bus;
  424.  
  425.     mutex_lock(&bus->mdio_lock);
  426.     bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
  427.     bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
  428.     mutex_unlock(&bus->mdio_lock);
  429. }
  430.  
  431. static inline u32
  432. ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  433. {
  434.     return priv->rmw(priv, reg, mask, val);
  435. }
  436.  
  437. static inline void
  438. ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
  439. {
  440.     priv->rmw(priv, reg, 0, val);
  441. }
  442.  
  443. static int
  444. ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
  445.         unsigned timeout)
  446. {
  447.     int i;
  448.  
  449.     for (i = 0; i < timeout; i++) {
  450.         u32 t;
  451.  
  452.         t = priv->read(priv, reg);
  453.         if ((t & mask) == val)
  454.             return 0;
  455.  
  456.         usleep_range(1000, 2000);
  457.     }
  458.  
  459.     return -ETIMEDOUT;
  460. }
  461.  
  462. static int
  463. ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
  464. {
  465.     unsigned mib_func;
  466.     int ret;
  467.  
  468.     lockdep_assert_held(&priv->mib_lock);
  469.  
  470.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  471.         mib_func = AR8327_REG_MIB_FUNC;
  472.     else
  473.         mib_func = AR8216_REG_MIB_FUNC;
  474.  
  475.     /* Capture the hardware statistics for all ports */
  476.     ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
  477.  
  478.     /* Wait for the capturing to complete. */
  479.     ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
  480.     if (ret)
  481.         goto out;
  482.  
  483.     ret = 0;
  484.  
  485. out:
  486.     return ret;
  487. }
  488.  
  489. static int
  490. ar8xxx_mib_capture(struct ar8xxx_priv *priv)
  491. {
  492.     return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
  493. }
  494.  
  495. static int
  496. ar8xxx_mib_flush(struct ar8xxx_priv *priv)
  497. {
  498.     return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
  499. }
  500.  
  501. static void
  502. ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
  503. {
  504.     unsigned int base;
  505.     u64 *mib_stats;
  506.     int i;
  507.  
  508.     WARN_ON(port >= priv->dev.ports);
  509.  
  510.     lockdep_assert_held(&priv->mib_lock);
  511.  
  512.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  513.         base = AR8327_REG_PORT_STATS_BASE(port);
  514.     else if (chip_is_ar8236(priv) ||
  515.          chip_is_ar8316(priv))
  516.         base = AR8236_REG_PORT_STATS_BASE(port);
  517.     else
  518.         base = AR8216_REG_PORT_STATS_BASE(port);
  519.  
  520.     mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
  521.     for (i = 0; i < priv->chip->num_mibs; i++) {
  522.         const struct ar8xxx_mib_desc *mib;
  523.         u64 t;
  524.  
  525.         mib = &priv->chip->mib_decs[i];
  526.         t = priv->read(priv, base + mib->offset);
  527.         if (mib->size == 2) {
  528.             u64 hi;
  529.  
  530.             hi = priv->read(priv, base + mib->offset + 4);
  531.             t |= hi << 32;
  532.         }
  533.  
  534.         if (flush)
  535.             mib_stats[i] = 0;
  536.         else
  537.             mib_stats[i] += t;
  538.     }
  539. }
  540.  
  541. static void
  542. ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
  543.               struct switch_port_link *link)
  544. {
  545.     u32 status;
  546.     u32 speed;
  547.  
  548.     memset(link, '\0', sizeof(*link));
  549.  
  550.     status = priv->chip->read_port_status(priv, port);
  551.  
  552.     link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
  553.     if (link->aneg) {
  554.         link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
  555.     } else {
  556.         link->link = true;
  557.  
  558.         if (priv->get_port_link) {
  559.             int err;
  560.  
  561.             err = priv->get_port_link(port);
  562.             if (err >= 0)
  563.                 link->link = !!err;
  564.         }
  565.     }
  566.  
  567.     if (!link->link)
  568.         return;
  569.  
  570.     link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
  571.     link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
  572.     link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
  573.  
  574.     speed = (status & AR8216_PORT_STATUS_SPEED) >>
  575.          AR8216_PORT_STATUS_SPEED_S;
  576.  
  577.     switch (speed) {
  578.     case AR8216_PORT_SPEED_10M:
  579.         link->speed = SWITCH_PORT_SPEED_10;
  580.         break;
  581.     case AR8216_PORT_SPEED_100M:
  582.         link->speed = SWITCH_PORT_SPEED_100;
  583.         break;
  584.     case AR8216_PORT_SPEED_1000M:
  585.         link->speed = SWITCH_PORT_SPEED_1000;
  586.         break;
  587.     default:
  588.         link->speed = SWITCH_PORT_SPEED_UNKNOWN;
  589.         break;
  590.     }
  591. }
  592.  
  593. static struct sk_buff *
  594. ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
  595. {
  596.     struct ar8xxx_priv *priv = dev->phy_ptr;
  597.     unsigned char *buf;
  598.  
  599.     if (unlikely(!priv))
  600.         goto error;
  601.  
  602.     if (!priv->vlan)
  603.         goto send;
  604.  
  605.     if (unlikely(skb_headroom(skb) < 2)) {
  606.         if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
  607.             goto error;
  608.     }
  609.  
  610.     buf = skb_push(skb, 2);
  611.     buf[0] = 0x10;
  612.     buf[1] = 0x80;
  613.  
  614. send:
  615.     return skb;
  616.  
  617. error:
  618.     dev_kfree_skb_any(skb);
  619.     return NULL;
  620. }
  621.  
  622. static void
  623. ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
  624. {
  625.     struct ar8xxx_priv *priv;
  626.     unsigned char *buf;
  627.     int port, vlan;
  628.  
  629.     priv = dev->phy_ptr;
  630.     if (!priv)
  631.         return;
  632.  
  633.     /* don't strip the header if vlan mode is disabled */
  634.     if (!priv->vlan)
  635.         return;
  636.  
  637.     /* strip header, get vlan id */
  638.     buf = skb->data;
  639.     skb_pull(skb, 2);
  640.  
  641.     /* check for vlan header presence */
  642.     if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
  643.         return;
  644.  
  645.     port = buf[0] & 0xf;
  646.  
  647.     /* no need to fix up packets coming from a tagged source */
  648.     if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  649.         return;
  650.  
  651.     /* lookup port vid from local table, the switch passes an invalid vlan id */
  652.     vlan = priv->vlan_id[priv->pvid[port]];
  653.  
  654.     buf[14 + 2] &= 0xf0;
  655.     buf[14 + 2] |= vlan >> 8;
  656.     buf[15 + 2] = vlan & 0xff;
  657. }
  658.  
  659. static int
  660. ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  661. {
  662.     int timeout = 20;
  663.     u32 t = 0;
  664.  
  665.     while (1) {
  666.         t = priv->read(priv, reg);
  667.         if ((t & mask) == val)
  668.             return 0;
  669.  
  670.         if (timeout-- <= 0)
  671.             break;
  672.  
  673.         udelay(10);
  674.     }
  675.  
  676.     pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
  677.            (unsigned int) reg, t, mask, val);
  678.     return -ETIMEDOUT;
  679. }
  680.  
  681. static void
  682. ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  683. {
  684.     if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
  685.         return;
  686.     if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
  687.         val &= AR8216_VTUDATA_MEMBER;
  688.         val |= AR8216_VTUDATA_VALID;
  689.         priv->write(priv, AR8216_REG_VTU_DATA, val);
  690.     }
  691.     op |= AR8216_VTU_ACTIVE;
  692.     priv->write(priv, AR8216_REG_VTU, op);
  693. }
  694.  
  695. static void
  696. ar8216_vtu_flush(struct ar8xxx_priv *priv)
  697. {
  698.     ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
  699. }
  700.  
  701. static void
  702. ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
  703. {
  704.     u32 op;
  705.  
  706.     u32 vid = priv->vlan_id[vlan];
  707.     u32 port_mask = priv->vlan_table[vlan];
  708.    
  709.     op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
  710.     ar8216_vtu_op(priv, op, port_mask);
  711. }
  712.  
  713. static int
  714. ar8216_atu_flush(struct ar8xxx_priv *priv)
  715. {
  716.     int ret;
  717.  
  718.     ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
  719.     if (!ret)
  720.         priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
  721.  
  722.     return ret;
  723. }
  724.  
  725. static u32
  726. ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
  727. {
  728.     return priv->read(priv, AR8216_REG_PORT_STATUS(port));
  729. }
  730.  
  731. static void
  732. ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  733. {
  734.     u32 header;
  735.     u32 egress, ingress;
  736.     u32 pvid;
  737.  
  738.     if (priv->vlan) {
  739.         pvid = priv->vlan_id[priv->pvid[port]];
  740.         if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  741.             egress = AR8216_OUT_ADD_VLAN;
  742.         else
  743.             egress = AR8216_OUT_STRIP_VLAN;
  744.         ingress = AR8216_IN_SECURE;
  745.     } else {
  746.         pvid = port;
  747.         egress = AR8216_OUT_KEEP;
  748.         ingress = AR8216_IN_PORT_ONLY;
  749.     }
  750.    
  751.    
  752.  
  753.     if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
  754.         header = AR8216_PORT_CTRL_HEADER;
  755.     else
  756.         header = 0;
  757.  
  758.     ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  759.            AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  760.            AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  761.            AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  762.            AR8216_PORT_CTRL_LEARN | header |
  763.            (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  764.            (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  765.  
  766.     ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
  767.            AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
  768.            AR8216_PORT_VLAN_DEFAULT_ID,
  769.            (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
  770.            (ingress << AR8216_PORT_VLAN_MODE_S) |
  771.            (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
  772. }
  773.  
  774. static int
  775. ar8216_hw_init(struct ar8xxx_priv *priv)
  776. {
  777.     return 0;
  778. }
  779.  
  780. static void
  781. ar8216_init_globals(struct ar8xxx_priv *priv)
  782. {
  783.     /* standard atheros magic */
  784.     priv->write(priv, 0x38, 0xc000050e);
  785.  
  786.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  787.            AR8216_GCTRL_MTU, 1518 + 8 + 2);
  788. }
  789.  
  790. static void
  791. ar8216_init_port(struct ar8xxx_priv *priv, int port)
  792. {
  793.     /* Enable port learning and tx */
  794.     priv->write(priv, AR8216_REG_PORT_CTRL(port),
  795.         AR8216_PORT_CTRL_LEARN |
  796.         (4 << AR8216_PORT_CTRL_STATE_S));
  797.  
  798.     priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
  799.  
  800.     if (port == AR8216_PORT_CPU) {
  801.         priv->write(priv, AR8216_REG_PORT_STATUS(port),
  802.             AR8216_PORT_STATUS_LINK_UP |
  803.             (ar8xxx_has_gige(priv) ?
  804.                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
  805.             AR8216_PORT_STATUS_TXMAC |
  806.             AR8216_PORT_STATUS_RXMAC |
  807.             (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
  808.             (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
  809.             AR8216_PORT_STATUS_DUPLEX);
  810.     } else {
  811.         priv->write(priv, AR8216_REG_PORT_STATUS(port),
  812.             AR8216_PORT_STATUS_LINK_AUTO);
  813.     }
  814. }
  815.  
  816. static const struct ar8xxx_chip ar8216_chip = {
  817.     .caps = AR8XXX_CAP_MIB_COUNTERS,
  818.  
  819.     .hw_init = ar8216_hw_init,
  820.     .init_globals = ar8216_init_globals,
  821.     .init_port = ar8216_init_port,
  822.     .setup_port = ar8216_setup_port,
  823.     .read_port_status = ar8216_read_port_status,
  824.     .atu_flush = ar8216_atu_flush,
  825.     .vtu_flush = ar8216_vtu_flush,
  826.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  827.  
  828.     .num_mibs = ARRAY_SIZE(ar8216_mibs),
  829.     .mib_decs = ar8216_mibs,
  830. };
  831.  
  832. static void
  833. ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  834. {
  835.     u32 egress, ingress;
  836.     u32 pvid;
  837.  
  838.     if (priv->vlan) {
  839.         pvid = priv->vlan_id[priv->pvid[port]];
  840.         if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  841.             egress = AR8216_OUT_ADD_VLAN;
  842.         else
  843.             egress = AR8216_OUT_STRIP_VLAN;
  844.         ingress = AR8216_IN_SECURE;
  845.     } else {
  846.         pvid = port;
  847.         egress = AR8216_OUT_KEEP;
  848.         ingress = AR8216_IN_PORT_ONLY;
  849.     }
  850.  
  851.     ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  852.            AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  853.            AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  854.            AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  855.            AR8216_PORT_CTRL_LEARN |
  856.            (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  857.            (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  858.  
  859.     ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
  860.            AR8236_PORT_VLAN_DEFAULT_ID,
  861.            (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
  862.  
  863.     ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
  864.            AR8236_PORT_VLAN2_VLAN_MODE |
  865.            AR8236_PORT_VLAN2_MEMBER,
  866.            (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
  867.            (members << AR8236_PORT_VLAN2_MEMBER_S));
  868. }
  869.  
  870. static int
  871. ar8236_hw_init(struct ar8xxx_priv *priv)
  872. {
  873.     int i;
  874.     struct mii_bus *bus;
  875.  
  876.     if (priv->initialized)
  877.         return 0;
  878.  
  879.     /* Initialize the PHYs */
  880.     bus = priv->mii_bus;
  881.     for (i = 0; i < 5; i++) {
  882.         mdiobus_write(bus, i, MII_ADVERTISE,
  883.                   ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  884.                   ADVERTISE_PAUSE_ASYM);
  885.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  886.     }
  887.     msleep(1000);
  888.  
  889.     priv->initialized = true;
  890.     return 0;
  891. }
  892.  
  893. static void
  894. ar8236_init_globals(struct ar8xxx_priv *priv)
  895. {
  896.     /* enable jumbo frames */
  897.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  898.            AR8316_GCTRL_MTU, 9018 + 8 + 2);
  899.  
  900.     /* Enable MIB counters */
  901.     ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  902.            (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  903.            AR8236_MIB_EN);
  904. }
  905.  
  906. static const struct ar8xxx_chip ar8236_chip = {
  907.     .caps = AR8XXX_CAP_MIB_COUNTERS,
  908.     .hw_init = ar8236_hw_init,
  909.     .init_globals = ar8236_init_globals,
  910.     .init_port = ar8216_init_port,
  911.     .setup_port = ar8236_setup_port,
  912.     .read_port_status = ar8216_read_port_status,
  913.     .atu_flush = ar8216_atu_flush,
  914.     .vtu_flush = ar8216_vtu_flush,
  915.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  916.  
  917.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  918.     .mib_decs = ar8236_mibs,
  919. };
  920.  
  921. static int
  922. ar8316_hw_init(struct ar8xxx_priv *priv)
  923. {
  924.     int i;
  925.     u32 val, newval;
  926.     struct mii_bus *bus;
  927.  
  928.     val = priv->read(priv, AR8316_REG_POSTRIP);
  929.  
  930.     if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  931.         if (priv->port4_phy) {
  932.             /* value taken from Ubiquiti RouterStation Pro */
  933.             newval = 0x81461bea;
  934.             pr_info("ar8316: Using port 4 as PHY\n");
  935.         } else {
  936.             newval = 0x01261be2;
  937.             pr_info("ar8316: Using port 4 as switch port\n");
  938.         }
  939.     } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
  940.         /* value taken from AVM Fritz!Box 7390 sources */
  941.         newval = 0x010e5b71;
  942.     } else {
  943.         /* no known value for phy interface */
  944.         pr_err("ar8316: unsupported mii mode: %d.\n",
  945.                priv->phy->interface);
  946.         return -EINVAL;
  947.     }
  948.  
  949.     if (val == newval)
  950.         goto out;
  951.  
  952.     priv->write(priv, AR8316_REG_POSTRIP, newval);
  953.  
  954.     if (priv->port4_phy &&
  955.         priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  956.         /* work around for phy4 rgmii mode */
  957.         ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
  958.         /* rx delay */
  959.         ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
  960.         /* tx delay */
  961.         ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
  962.         msleep(1000);
  963.     }
  964.  
  965.     /* Initialize the ports */
  966.     bus = priv->mii_bus;
  967.     for (i = 0; i < 5; i++) {
  968.         /* initialize the port itself */
  969.         mdiobus_write(bus, i, MII_ADVERTISE,
  970.             ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  971.         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  972.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  973.     }
  974.  
  975.     msleep(1000);
  976.  
  977. out:
  978.     priv->initialized = true;
  979.     return 0;
  980. }
  981.  
  982. static void
  983. ar8316_init_globals(struct ar8xxx_priv *priv)
  984. {
  985.     /* standard atheros magic */
  986.     priv->write(priv, 0x38, 0xc000050e);
  987.  
  988.     /* enable cpu port to receive multicast and broadcast frames */
  989.     priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
  990.  
  991.     /* enable jumbo frames */
  992.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  993.            AR8316_GCTRL_MTU, 9018 + 8 + 2);
  994.  
  995.     /* Enable MIB counters */
  996.     ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  997.            (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  998.            AR8236_MIB_EN);
  999. }
  1000.  
  1001. static const struct ar8xxx_chip ar8316_chip = {
  1002.     .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  1003.     .hw_init = ar8316_hw_init,
  1004.     .init_globals = ar8316_init_globals,
  1005.     .init_port = ar8216_init_port,
  1006.     .setup_port = ar8216_setup_port,
  1007.     .read_port_status = ar8216_read_port_status,
  1008.     .atu_flush = ar8216_atu_flush,
  1009.     .vtu_flush = ar8216_vtu_flush,
  1010.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  1011.  
  1012.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1013.     .mib_decs = ar8236_mibs,
  1014. };
  1015.  
  1016. static u32
  1017. ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
  1018. {
  1019.     u32 t;
  1020.  
  1021.     if (!cfg)
  1022.         return 0;
  1023.  
  1024.     t = 0;
  1025.     switch (cfg->mode) {
  1026.     case AR8327_PAD_NC:
  1027.         break;
  1028.  
  1029.     case AR8327_PAD_MAC2MAC_MII:
  1030.         t = AR8327_PAD_MAC_MII_EN;
  1031.         if (cfg->rxclk_sel)
  1032.             t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
  1033.         if (cfg->txclk_sel)
  1034.             t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
  1035.         break;
  1036.  
  1037.     case AR8327_PAD_MAC2MAC_GMII:
  1038.         t = AR8327_PAD_MAC_GMII_EN;
  1039.         if (cfg->rxclk_sel)
  1040.             t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
  1041.         if (cfg->txclk_sel)
  1042.             t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
  1043.         break;
  1044.  
  1045.     case AR8327_PAD_MAC_SGMII:
  1046.         t = AR8327_PAD_SGMII_EN;
  1047.  
  1048.         /*
  1049.          * WAR for the QUalcomm Atheros AP136 board.
  1050.          * It seems that RGMII TX/RX delay settings needs to be
  1051.          * applied for SGMII mode as well, The ethernet is not
  1052.          * reliable without this.
  1053.          */
  1054.         t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  1055.         t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  1056.         if (cfg->rxclk_delay_en)
  1057.             t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  1058.         if (cfg->txclk_delay_en)
  1059.             t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  1060.  
  1061.         if (cfg->sgmii_delay_en)
  1062.             t |= AR8327_PAD_SGMII_DELAY_EN;
  1063.  
  1064.         break;
  1065.  
  1066.     case AR8327_PAD_MAC2PHY_MII:
  1067.         t = AR8327_PAD_PHY_MII_EN;
  1068.         if (cfg->rxclk_sel)
  1069.             t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
  1070.         if (cfg->txclk_sel)
  1071.             t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
  1072.         break;
  1073.  
  1074.     case AR8327_PAD_MAC2PHY_GMII:
  1075.         t = AR8327_PAD_PHY_GMII_EN;
  1076.         if (cfg->pipe_rxclk_sel)
  1077.             t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
  1078.         if (cfg->rxclk_sel)
  1079.             t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
  1080.         if (cfg->txclk_sel)
  1081.             t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
  1082.         break;
  1083.  
  1084.     case AR8327_PAD_MAC_RGMII:
  1085.         t = AR8327_PAD_RGMII_EN;
  1086.         t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  1087.         t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  1088.         if (cfg->rxclk_delay_en)
  1089.             t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  1090.         if (cfg->txclk_delay_en)
  1091.             t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  1092.         break;
  1093.  
  1094.     case AR8327_PAD_PHY_GMII:
  1095.         t = AR8327_PAD_PHYX_GMII_EN;
  1096.         break;
  1097.  
  1098.     case AR8327_PAD_PHY_RGMII:
  1099.         t = AR8327_PAD_PHYX_RGMII_EN;
  1100.         break;
  1101.  
  1102.     case AR8327_PAD_PHY_MII:
  1103.         t = AR8327_PAD_PHYX_MII_EN;
  1104.         break;
  1105.     }
  1106.  
  1107.     return t;
  1108. }
  1109.  
  1110. static void
  1111. ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
  1112. {
  1113.     switch (priv->chip_rev) {
  1114.     case 1:
  1115.         /* For 100M waveform */
  1116.         ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
  1117.         /* Turn on Gigabit clock */
  1118.         ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
  1119.         break;
  1120.  
  1121.     case 2:
  1122.         ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
  1123.         ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
  1124.         /* fallthrough */
  1125.     case 4:
  1126.         ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
  1127.         ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
  1128.  
  1129.         ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
  1130.         ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
  1131.         ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
  1132.         break;
  1133.     }
  1134. }
  1135.  
  1136. static u32
  1137. ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
  1138. {
  1139.     u32 t;
  1140.  
  1141.     if (!cfg->force_link)
  1142.         return AR8216_PORT_STATUS_LINK_AUTO;
  1143.  
  1144.     t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
  1145.     t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
  1146.     t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
  1147.     t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
  1148.  
  1149.     switch (cfg->speed) {
  1150.     case AR8327_PORT_SPEED_10:
  1151.         t |= AR8216_PORT_SPEED_10M;
  1152.         break;
  1153.     case AR8327_PORT_SPEED_100:
  1154.         t |= AR8216_PORT_SPEED_100M;
  1155.         break;
  1156.     case AR8327_PORT_SPEED_1000:
  1157.         t |= AR8216_PORT_SPEED_1000M;
  1158.         break;
  1159.     }
  1160.  
  1161.     return t;
  1162. }
  1163.  
  1164. #define AR8327_LED_ENTRY(_num, _reg, _shift) \
  1165.     [_num] = { .reg = (_reg), .shift = (_shift) }
  1166.  
  1167. static const struct ar8327_led_entry
  1168. ar8327_led_map[AR8327_NUM_LEDS] = {
  1169.     AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
  1170.     AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
  1171.     AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
  1172.  
  1173.     AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
  1174.     AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
  1175.     AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
  1176.  
  1177.     AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
  1178.     AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
  1179.     AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
  1180.  
  1181.     AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
  1182.     AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
  1183.     AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
  1184.  
  1185.     AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
  1186.     AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
  1187.     AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
  1188. };
  1189.  
  1190. static void
  1191. ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
  1192.                enum ar8327_led_pattern pattern)
  1193. {
  1194.     const struct ar8327_led_entry *entry;
  1195.  
  1196.     entry = &ar8327_led_map[led_num];
  1197.     ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
  1198.            (3 << entry->shift), pattern << entry->shift);
  1199. }
  1200.  
  1201. static void
  1202. ar8327_led_work_func(struct work_struct *work)
  1203. {
  1204.     struct ar8327_led *aled;
  1205.     u8 pattern;
  1206.  
  1207.     aled = container_of(work, struct ar8327_led, led_work);
  1208.  
  1209.     spin_lock(&aled->lock);
  1210.     pattern = aled->pattern;
  1211.     spin_unlock(&aled->lock);
  1212.  
  1213.     ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
  1214.                    pattern);
  1215. }
  1216.  
  1217. static void
  1218. ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
  1219. {
  1220.     if (aled->pattern == pattern)
  1221.         return;
  1222.  
  1223.     aled->pattern = pattern;
  1224.     schedule_work(&aled->led_work);
  1225. }
  1226.  
  1227. static inline struct ar8327_led *
  1228. led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
  1229. {
  1230.     return container_of(led_cdev, struct ar8327_led, cdev);
  1231. }
  1232.  
  1233. static int
  1234. ar8327_led_blink_set(struct led_classdev *led_cdev,
  1235.              unsigned long *delay_on,
  1236.              unsigned long *delay_off)
  1237. {
  1238.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1239.  
  1240.     if (*delay_on == 0 && *delay_off == 0) {
  1241.         *delay_on = 125;
  1242.         *delay_off = 125;
  1243.     }
  1244.  
  1245.     if (*delay_on != 125 || *delay_off != 125) {
  1246.         /*
  1247.          * The hardware only supports blinking at 4Hz. Fall back
  1248.          * to software implementation in other cases.
  1249.          */
  1250.         return -EINVAL;
  1251.     }
  1252.  
  1253.     spin_lock(&aled->lock);
  1254.  
  1255.     aled->enable_hw_mode = false;
  1256.     ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
  1257.  
  1258.     spin_unlock(&aled->lock);
  1259.  
  1260.     return 0;
  1261. }
  1262.  
  1263. static void
  1264. ar8327_led_set_brightness(struct led_classdev *led_cdev,
  1265.               enum led_brightness brightness)
  1266. {
  1267.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1268.     u8 pattern;
  1269.     bool active;
  1270.  
  1271.     active = (brightness != LED_OFF);
  1272.     active ^= aled->active_low;
  1273.  
  1274.     pattern = (active) ? AR8327_LED_PATTERN_ON :
  1275.                  AR8327_LED_PATTERN_OFF;
  1276.  
  1277.     spin_lock(&aled->lock);
  1278.  
  1279.     aled->enable_hw_mode = false;
  1280.     ar8327_led_schedule_change(aled, pattern);
  1281.  
  1282.     spin_unlock(&aled->lock);
  1283. }
  1284.  
  1285. static ssize_t
  1286. ar8327_led_enable_hw_mode_show(struct device *dev,
  1287.                    struct device_attribute *attr,
  1288.                    char *buf)
  1289. {
  1290.     struct led_classdev *led_cdev = dev_get_drvdata(dev);
  1291.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1292.     ssize_t ret = 0;
  1293.  
  1294.     spin_lock(&aled->lock);
  1295.     ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
  1296.     spin_unlock(&aled->lock);
  1297.  
  1298.     return ret;
  1299. }
  1300.  
  1301. static ssize_t
  1302. ar8327_led_enable_hw_mode_store(struct device *dev,
  1303.                 struct device_attribute *attr,
  1304.                 const char *buf,
  1305.                 size_t size)
  1306. {
  1307.         struct led_classdev *led_cdev = dev_get_drvdata(dev);
  1308.     struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
  1309.     u8 pattern;
  1310.     u8 value;
  1311.     int ret;
  1312.  
  1313.     ret = kstrtou8(buf, 10, &value);
  1314.     if (ret < 0)
  1315.         return -EINVAL;
  1316.  
  1317.     spin_lock(&aled->lock);
  1318.  
  1319.     aled->enable_hw_mode = !!value;
  1320.     if (aled->enable_hw_mode)
  1321.         pattern = AR8327_LED_PATTERN_RULE;
  1322.     else
  1323.         pattern = AR8327_LED_PATTERN_OFF;
  1324.  
  1325.     ar8327_led_schedule_change(aled, pattern);
  1326.  
  1327.     spin_unlock(&aled->lock);
  1328.  
  1329.     return size;
  1330. }
  1331.  
  1332. static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
  1333.            ar8327_led_enable_hw_mode_show,
  1334.            ar8327_led_enable_hw_mode_store);
  1335.  
  1336. static int
  1337. ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
  1338. {
  1339.     int ret;
  1340.  
  1341.     ret = led_classdev_register(NULL, &aled->cdev);
  1342.     if (ret < 0)
  1343.         return ret;
  1344.  
  1345.     if (aled->mode == AR8327_LED_MODE_HW) {
  1346.         ret = device_create_file(aled->cdev.dev,
  1347.                      &dev_attr_enable_hw_mode);
  1348.         if (ret)
  1349.             goto err_unregister;
  1350.     }
  1351.  
  1352.     return 0;
  1353.  
  1354. err_unregister:
  1355.     led_classdev_unregister(&aled->cdev);
  1356.     return ret;
  1357. }
  1358.  
  1359. static void
  1360. ar8327_led_unregister(struct ar8327_led *aled)
  1361. {
  1362.     if (aled->mode == AR8327_LED_MODE_HW)
  1363.         device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
  1364.  
  1365.     led_classdev_unregister(&aled->cdev);
  1366.     cancel_work_sync(&aled->led_work);
  1367. }
  1368.  
  1369. static int
  1370. ar8327_led_create(struct ar8xxx_priv *priv,
  1371.           const struct ar8327_led_info *led_info)
  1372. {
  1373.     struct ar8327_data *data = &priv->chip_data.ar8327;
  1374.     struct ar8327_led *aled;
  1375.     int ret;
  1376.  
  1377.     if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
  1378.         return 0;
  1379.  
  1380.     if (!led_info->name)
  1381.         return -EINVAL;
  1382.  
  1383.     if (led_info->led_num >= AR8327_NUM_LEDS)
  1384.         return -EINVAL;
  1385.  
  1386.     aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
  1387.                GFP_KERNEL);
  1388.     if (!aled)
  1389.         return -ENOMEM;
  1390.  
  1391.     aled->sw_priv = priv;
  1392.     aled->led_num = led_info->led_num;
  1393.     aled->active_low = led_info->active_low;
  1394.     aled->mode = led_info->mode;
  1395.  
  1396.     if (aled->mode == AR8327_LED_MODE_HW)
  1397.         aled->enable_hw_mode = true;
  1398.  
  1399.     aled->name = (char *)(aled + 1);
  1400.     strcpy(aled->name, led_info->name);
  1401.  
  1402.     aled->cdev.name = aled->name;
  1403.     aled->cdev.brightness_set = ar8327_led_set_brightness;
  1404.     aled->cdev.blink_set = ar8327_led_blink_set;
  1405.     aled->cdev.default_trigger = led_info->default_trigger;
  1406.  
  1407.     spin_lock_init(&aled->lock);
  1408.     mutex_init(&aled->mutex);
  1409.     INIT_WORK(&aled->led_work, ar8327_led_work_func);
  1410.  
  1411.     ret = ar8327_led_register(priv, aled);
  1412.     if (ret)
  1413.         goto err_free;
  1414.  
  1415.     data->leds[data->num_leds++] = aled;
  1416.  
  1417.     return 0;
  1418.  
  1419. err_free:
  1420.     kfree(aled);
  1421.     return ret;
  1422. }
  1423.  
  1424. static void
  1425. ar8327_led_destroy(struct ar8327_led *aled)
  1426. {
  1427.     ar8327_led_unregister(aled);
  1428.     kfree(aled);
  1429. }
  1430.  
  1431. static void
  1432. ar8327_leds_init(struct ar8xxx_priv *priv)
  1433. {
  1434.     struct ar8327_data *data;
  1435.     unsigned i;
  1436.  
  1437.     if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
  1438.         return;
  1439.  
  1440.     data = &priv->chip_data.ar8327;
  1441.  
  1442.     for (i = 0; i < data->num_leds; i++) {
  1443.         struct ar8327_led *aled;
  1444.  
  1445.         aled = data->leds[i];
  1446.  
  1447.         if (aled->enable_hw_mode)
  1448.             aled->pattern = AR8327_LED_PATTERN_RULE;
  1449.         else
  1450.             aled->pattern = AR8327_LED_PATTERN_OFF;
  1451.  
  1452.         ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
  1453.     }
  1454. }
  1455.  
  1456. static void
  1457. ar8327_leds_cleanup(struct ar8xxx_priv *priv)
  1458. {
  1459.     struct ar8327_data *data = &priv->chip_data.ar8327;
  1460.     unsigned i;
  1461.  
  1462.     if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
  1463.         return;
  1464.  
  1465.     for (i = 0; i < data->num_leds; i++) {
  1466.         struct ar8327_led *aled;
  1467.  
  1468.         aled = data->leds[i];
  1469.         ar8327_led_destroy(aled);
  1470.     }
  1471.  
  1472.     kfree(data->leds);
  1473. }
  1474.  
  1475. static int
  1476. ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
  1477.                struct ar8327_platform_data *pdata)
  1478. {
  1479.     struct ar8327_led_cfg *led_cfg;
  1480.     struct ar8327_data *data;
  1481.     u32 pos, new_pos;
  1482.     u32 t;
  1483.  
  1484.     if (!pdata)
  1485.         return -EINVAL;
  1486.  
  1487.     priv->get_port_link = pdata->get_port_link;
  1488.  
  1489.     data = &priv->chip_data.ar8327;
  1490.  
  1491.     data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
  1492.     data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
  1493.  
  1494.     t = ar8327_get_pad_cfg(pdata->pad0_cfg);
  1495.     if (chip_is_ar8337(priv))
  1496.         t |= AR8337_PAD_MAC06_EXCHANGE_EN;
  1497.  
  1498.     priv->write(priv, AR8327_REG_PAD0_MODE, t);
  1499.     t = ar8327_get_pad_cfg(pdata->pad5_cfg);
  1500.     priv->write(priv, AR8327_REG_PAD5_MODE, t);
  1501.     t = ar8327_get_pad_cfg(pdata->pad6_cfg);
  1502.     priv->write(priv, AR8327_REG_PAD6_MODE, t);
  1503.  
  1504.     pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
  1505.     new_pos = pos;
  1506.  
  1507.     led_cfg = pdata->led_cfg;
  1508.     if (led_cfg) {
  1509.         if (led_cfg->open_drain)
  1510.             new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
  1511.         else
  1512.             new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
  1513.  
  1514.         priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
  1515.         priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
  1516.         priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
  1517.         priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
  1518.  
  1519.         if (new_pos != pos)
  1520.             new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
  1521.     }
  1522.  
  1523.     if (pdata->sgmii_cfg) {
  1524.         t = pdata->sgmii_cfg->sgmii_ctrl;
  1525.         if (priv->chip_rev == 1)
  1526.             t |= AR8327_SGMII_CTRL_EN_PLL |
  1527.                  AR8327_SGMII_CTRL_EN_RX |
  1528.                  AR8327_SGMII_CTRL_EN_TX;
  1529.         else
  1530.             t &= ~(AR8327_SGMII_CTRL_EN_PLL |
  1531.                    AR8327_SGMII_CTRL_EN_RX |
  1532.                    AR8327_SGMII_CTRL_EN_TX);
  1533.  
  1534.         priv->write(priv, AR8327_REG_SGMII_CTRL, t);
  1535.  
  1536.         if (pdata->sgmii_cfg->serdes_aen)
  1537.             new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
  1538.         else
  1539.             new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
  1540.     }
  1541.  
  1542.     priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
  1543.  
  1544.     if (pdata->leds && pdata->num_leds) {
  1545.         int i;
  1546.  
  1547.         data->leds = kzalloc(pdata->num_leds * sizeof(void *),
  1548.                      GFP_KERNEL);
  1549.         if (!data->leds)
  1550.             return -ENOMEM;
  1551.  
  1552.         for (i = 0; i < pdata->num_leds; i++)
  1553.             ar8327_led_create(priv, &pdata->leds[i]);
  1554.     }
  1555.  
  1556.     return 0;
  1557. }
  1558.  
  1559. #ifdef CONFIG_OF
  1560. static int
  1561. ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
  1562. {
  1563.     const __be32 *paddr;
  1564.     int len;
  1565.     int i;
  1566.  
  1567.     paddr = of_get_property(np, "qca,ar8327-initvals", &len);
  1568.     if (!paddr || len < (2 * sizeof(*paddr)))
  1569.         return -EINVAL;
  1570.  
  1571.     len /= sizeof(*paddr);
  1572.  
  1573.     for (i = 0; i < len - 1; i += 2) {
  1574.         u32 reg;
  1575.         u32 val;
  1576.  
  1577.         reg = be32_to_cpup(paddr + i);
  1578.         val = be32_to_cpup(paddr + i + 1);
  1579.  
  1580.         switch (reg) {
  1581.         case AR8327_REG_PORT_STATUS(0):
  1582.             priv->chip_data.ar8327.port0_status = val;
  1583.             break;
  1584.         case AR8327_REG_PORT_STATUS(6):
  1585.             priv->chip_data.ar8327.port6_status = val;
  1586.             break;
  1587.         default:
  1588.             priv->write(priv, reg, val);
  1589.             break;
  1590.         }
  1591.     }
  1592.  
  1593.     return 0;
  1594. }
  1595. #else
  1596. static inline int
  1597. ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
  1598. {
  1599.     return -EINVAL;
  1600. }
  1601. #endif
  1602.  
  1603. static int
  1604. ar8327_hw_init(struct ar8xxx_priv *priv)
  1605. {
  1606.     struct mii_bus *bus;
  1607.     int ret;
  1608.     int i;
  1609.  
  1610.     if (priv->phy->dev.of_node)
  1611.         ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
  1612.     else
  1613.         ret = ar8327_hw_config_pdata(priv,
  1614.                          priv->phy->dev.platform_data);
  1615.  
  1616.     if (ret)
  1617.         return ret;
  1618.  
  1619.     ar8327_leds_init(priv);
  1620.  
  1621.     bus = priv->mii_bus;
  1622.     for (i = 0; i < AR8327_NUM_PHYS; i++) {
  1623.         ar8327_phy_fixup(priv, i);
  1624.  
  1625.         /* start aneg on the PHY */
  1626.         mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
  1627.                              ADVERTISE_PAUSE_CAP |
  1628.                              ADVERTISE_PAUSE_ASYM);
  1629.         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  1630.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  1631.     }
  1632.  
  1633.     msleep(1000);
  1634.  
  1635.     return 0;
  1636. }
  1637.  
  1638. static void
  1639. ar8327_cleanup(struct ar8xxx_priv *priv)
  1640. {
  1641.     ar8327_leds_cleanup(priv);
  1642. }
  1643.  
  1644. static void
  1645. ar8327_init_globals(struct ar8xxx_priv *priv)
  1646. {
  1647.     u32 t;
  1648.  
  1649.     /* enable CPU port and disable mirror port */
  1650.     t = AR8327_FWD_CTRL0_CPU_PORT_EN |
  1651.         AR8327_FWD_CTRL0_MIRROR_PORT;
  1652.     priv->write(priv, AR8327_REG_FWD_CTRL0, t);
  1653.  
  1654.     /* forward multicast and broadcast frames to CPU */
  1655.     t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
  1656.         (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
  1657.         (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
  1658.     priv->write(priv, AR8327_REG_FWD_CTRL1, t);
  1659.  
  1660.     /* enable jumbo frames */
  1661.     ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
  1662.            AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
  1663.  
  1664.     /* Enable MIB counters */
  1665.     ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
  1666.                AR8327_MODULE_EN_MIB);
  1667. }
  1668.  
  1669. static void
  1670. ar8327_init_port(struct ar8xxx_priv *priv, int port)
  1671. {
  1672.     u32 t;
  1673.  
  1674.     if (port == AR8216_PORT_CPU)
  1675.         t = priv->chip_data.ar8327.port0_status;
  1676.     else if (port == 6)
  1677.         t = priv->chip_data.ar8327.port6_status;
  1678.     else
  1679.         t = AR8216_PORT_STATUS_LINK_AUTO;
  1680.  
  1681.     priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
  1682.     priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
  1683.  
  1684.     t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
  1685.     t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
  1686.     priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
  1687.  
  1688.     t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
  1689.     priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
  1690.  
  1691.     t = AR8327_PORT_LOOKUP_LEARN;
  1692.     t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
  1693.     priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
  1694. }
  1695.  
  1696. static u32
  1697. ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
  1698. {
  1699.     return priv->read(priv, AR8327_REG_PORT_STATUS(port));
  1700. }
  1701.  
  1702. static int
  1703. ar8327_atu_flush(struct ar8xxx_priv *priv)
  1704. {
  1705.     int ret;
  1706.  
  1707.     ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
  1708.                   AR8327_ATU_FUNC_BUSY, 0);
  1709.     if (!ret)
  1710.         priv->write(priv, AR8327_REG_ATU_FUNC,
  1711.                 AR8327_ATU_FUNC_OP_FLUSH);
  1712.  
  1713.     return ret;
  1714. }
  1715.  
  1716. static void
  1717. ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  1718. {
  1719.     if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
  1720.                 AR8327_VTU_FUNC1_BUSY, 0))
  1721.         return;
  1722.  
  1723.     if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
  1724.         priv->write(priv, AR8327_REG_VTU_FUNC0, val);
  1725.  
  1726.     op |= AR8327_VTU_FUNC1_BUSY;
  1727.     priv->write(priv, AR8327_REG_VTU_FUNC1, op);
  1728. }
  1729.  
  1730. static void
  1731. ar8327_vtu_flush(struct ar8xxx_priv *priv)
  1732. {
  1733.     ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
  1734. }
  1735.  
  1736. static void
  1737. ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
  1738. {
  1739.     u32 op;
  1740.     u32 val;
  1741.     int i;
  1742.    
  1743.     u32 vid = priv->vlan_id[vlan];
  1744.     u32 port_mask = priv->vlan_table[vlan];
  1745.     u32 tagged = priv->chip_data.ar8327.vlan_tagged[vlan];
  1746.    
  1747.     op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
  1748.     val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
  1749.     for (i = 0; i < AR8327_NUM_PORTS; i++) {
  1750.         u32 mode;
  1751.  
  1752.         if ((port_mask & BIT(i)) == 0)
  1753.             mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
  1754.         else if (priv->vlan == 0)
  1755.             mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
  1756.         else if (tagged & BIT(i))
  1757.             mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
  1758.         else
  1759.             mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
  1760.  
  1761.         val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
  1762.     }
  1763.     ar8327_vtu_op(priv, op, val);
  1764. }
  1765.  
  1766. static void
  1767. ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  1768. {
  1769.     u32 t;
  1770.     u32 mode;
  1771.     u32 ingress;
  1772.     u32 pvid;
  1773.    
  1774.     if (priv->vlan) {
  1775.         pvid = priv->vlan_id[priv->pvid[port]];
  1776.         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
  1777.         ingress = AR8216_IN_SECURE;
  1778.     } else {
  1779.         pvid = port;
  1780.         mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
  1781.         ingress = AR8216_IN_PORT_ONLY;
  1782.     }
  1783.  
  1784.     t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
  1785.     t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
  1786.     priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
  1787.  
  1788.     t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
  1789.     t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
  1790.     priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
  1791.  
  1792.     t = members;
  1793.     t |= AR8327_PORT_LOOKUP_LEARN;
  1794.     t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
  1795.     t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
  1796.     priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
  1797. }
  1798.  
  1799. static const struct ar8xxx_chip ar8327_chip = {
  1800.     .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  1801.     .hw_init = ar8327_hw_init,
  1802.     .cleanup = ar8327_cleanup,
  1803.     .init_globals = ar8327_init_globals,
  1804.     .init_port = ar8327_init_port,
  1805.     .setup_port = ar8327_setup_port,
  1806.     .read_port_status = ar8327_read_port_status,
  1807.     .atu_flush = ar8327_atu_flush,
  1808.     .vtu_flush = ar8327_vtu_flush,
  1809.     .vtu_load_vlan = ar8327_vtu_load_vlan,
  1810.  
  1811.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1812.     .mib_decs = ar8236_mibs,
  1813. };
  1814.  
  1815. static int
  1816. ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1817.            struct switch_val *val)
  1818. {
  1819.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1820.     priv->vlan = !!val->value.i;
  1821.     return 0;
  1822. }
  1823.  
  1824. static int
  1825. ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1826.            struct switch_val *val)
  1827. {
  1828.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1829.     val->value.i = priv->vlan;
  1830.     return 0;
  1831. }
  1832.  
  1833.  
  1834. static int
  1835. ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
  1836. {
  1837.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1838.  
  1839.     /* make sure no invalid PVIDs get set */
  1840.  
  1841.     if (vlan >= dev->vlans)
  1842.         return -EINVAL;
  1843.  
  1844.     priv->pvid[port] = vlan;
  1845.     return 0;
  1846. }
  1847.  
  1848. static int
  1849. ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
  1850. {
  1851.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1852.     *vlan = priv->pvid[port];
  1853.     return 0;
  1854. }
  1855.  
  1856. static int
  1857. ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1858.           struct switch_val *val)
  1859. {
  1860.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1861.     priv->vlan_id[val->port_vlan] = val->value.i;
  1862.     return 0;
  1863. }
  1864.  
  1865. static int
  1866. ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1867.           struct switch_val *val)
  1868. {
  1869.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1870.     val->value.i = priv->vlan_id[val->port_vlan];
  1871.     return 0;
  1872. }
  1873.  
  1874. static int
  1875. ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
  1876.             struct switch_port_link *link)
  1877. {
  1878.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1879.  
  1880.     ar8216_read_port_link(priv, port, link);
  1881.     return 0;
  1882. }
  1883.  
  1884. static int
  1885. ar8xxx_sw_get_ports(struct switch_val *val, int ports, u8 port_mask, u8 tagged)
  1886. {
  1887.     int i;
  1888.     val->len = 0;
  1889.     for (i = 0; i < ports; i++) {
  1890.         struct switch_port *p;
  1891.  
  1892.         if (!(port_mask & BIT(i)))
  1893.             continue;
  1894.  
  1895.         p = &val->value.ports[val->len++];
  1896.         p->id = i;
  1897.         if (tagged & BIT(i))
  1898.             p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
  1899.         else
  1900.             p->flags = 0;
  1901.     }
  1902.     return 0;
  1903. }
  1904.  
  1905. static int
  1906. ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  1907. {
  1908.     int ports = dev->ports;
  1909.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1910.     u8 port_mask = priv->vlan_table[val->port_vlan];
  1911.     u8 tagged = priv->chip_data.ar8216.vlan_tagged;
  1912.    
  1913.     return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
  1914. }
  1915.  
  1916. static int
  1917. ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  1918. {
  1919.     int ports = dev->ports;
  1920.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1921.     u8 port_mask = priv->vlan_table[val->port_vlan];
  1922.     u8 tagged = priv->chip_data.ar8327.vlan_tagged[val->port_vlan];
  1923.    
  1924.     return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
  1925. }
  1926.  
  1927. static int
  1928. ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  1929. {
  1930.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1931.     u8 *vt = &priv->vlan_table[val->port_vlan];
  1932.     u8 *tagged = &priv->chip_data.ar8216.vlan_tagged;
  1933.    
  1934.     int i, j;
  1935.  
  1936.     *vt = 0;
  1937.     for (i = 0; i < val->len; i++) {
  1938.         struct switch_port *p = &val->value.ports[i];
  1939.  
  1940.         if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
  1941.            
  1942.             /* if port was untagged before then
  1943.              * remove him from other vlans */
  1944.             if(*tagged & BIT(p->id)){
  1945.                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1946.                     if (j == val->port_vlan)
  1947.                         continue;
  1948.                
  1949.                     priv->vlan_table[j] &= ~(BIT(p->id));
  1950.                 }
  1951.             }
  1952.            
  1953.             *tagged |= BIT(p->id);
  1954.         } else {
  1955.             *tagged &= ~(BIT(p->id));
  1956.             priv->pvid[p->id] = val->port_vlan;
  1957.            
  1958.             /* make sure that an untagged port does not
  1959.             * appear in other vlans */
  1960.             for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1961.                 if (j == val->port_vlan)
  1962.                     continue;
  1963.                
  1964.                 priv->vlan_table[j] &= ~(BIT(p->id));
  1965.             }
  1966.         }
  1967.  
  1968.         *vt |= BIT(p->id);
  1969.     }
  1970.     return 0;
  1971. }
  1972.  
  1973. static int
  1974. ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  1975. {
  1976.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1977.     u8 *vt = &priv->vlan_table[val->port_vlan];
  1978.     u8 *vlan_tagged = priv->chip_data.ar8327.vlan_tagged;
  1979.     u8 *tagged = &vlan_tagged[val->port_vlan];
  1980.    
  1981.     int i, j;
  1982.  
  1983.     *vt = 0;
  1984.     *tagged = 0;
  1985.     for (i = 0; i < val->len; i++) {
  1986.         struct switch_port *p = &val->value.ports[i];
  1987.  
  1988.         if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
  1989.             *tagged |= BIT(p->id);
  1990.         } else {
  1991.             priv->pvid[p->id] = val->port_vlan;
  1992.            
  1993.             /* make sure that an untagged port does not
  1994.             * appear in other vlans */
  1995.             for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1996.                 if (j == val->port_vlan)
  1997.                     continue;
  1998.                
  1999.                 // skip tagged
  2000.                 if(vlan_tagged[j] & BIT(p->id))
  2001.                     continue;
  2002.                
  2003.                 // remove port
  2004.                 priv->vlan_table[j] &= ~(BIT(p->id));
  2005.             }
  2006.         }
  2007.  
  2008.         *vt |= BIT(p->id);
  2009.     }
  2010.     return 0;
  2011. }
  2012.  
  2013. static void
  2014. ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
  2015. {
  2016.     int port;
  2017.  
  2018.     /* reset all mirror registers */
  2019.     ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
  2020.            AR8327_FWD_CTRL0_MIRROR_PORT,
  2021.            (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
  2022.     for (port = 0; port < AR8327_NUM_PORTS; port++) {
  2023.         ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
  2024.                AR8327_PORT_LOOKUP_ING_MIRROR_EN,
  2025.                0);
  2026.  
  2027.         ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
  2028.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
  2029.                0);
  2030.     }
  2031.  
  2032.     /* now enable mirroring if necessary */
  2033.     if (priv->source_port >= AR8327_NUM_PORTS ||
  2034.         priv->monitor_port >= AR8327_NUM_PORTS ||
  2035.         priv->source_port == priv->monitor_port) {
  2036.         return;
  2037.     }
  2038.  
  2039.     ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
  2040.            AR8327_FWD_CTRL0_MIRROR_PORT,
  2041.            (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
  2042.  
  2043.     if (priv->mirror_rx)
  2044.         ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
  2045.                AR8327_PORT_LOOKUP_ING_MIRROR_EN,
  2046.                AR8327_PORT_LOOKUP_ING_MIRROR_EN);
  2047.  
  2048.     if (priv->mirror_tx)
  2049.         ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
  2050.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
  2051.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
  2052. }
  2053.  
  2054. static void
  2055. ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
  2056. {
  2057.     int port;
  2058.  
  2059.     /* reset all mirror registers */
  2060.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  2061.            AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  2062.            (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  2063.     for (port = 0; port < AR8216_NUM_PORTS; port++) {
  2064.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  2065.                AR8216_PORT_CTRL_MIRROR_RX,
  2066.                0);
  2067.  
  2068.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  2069.                AR8216_PORT_CTRL_MIRROR_TX,
  2070.                0);
  2071.     }
  2072.  
  2073.     /* now enable mirroring if necessary */
  2074.     if (priv->source_port >= AR8216_NUM_PORTS ||
  2075.         priv->monitor_port >= AR8216_NUM_PORTS ||
  2076.         priv->source_port == priv->monitor_port) {
  2077.         return;
  2078.     }
  2079.  
  2080.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  2081.            AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  2082.            (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  2083.  
  2084.     if (priv->mirror_rx)
  2085.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  2086.                AR8216_PORT_CTRL_MIRROR_RX,
  2087.                AR8216_PORT_CTRL_MIRROR_RX);
  2088.  
  2089.     if (priv->mirror_tx)
  2090.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  2091.                AR8216_PORT_CTRL_MIRROR_TX,
  2092.                AR8216_PORT_CTRL_MIRROR_TX);
  2093. }
  2094.  
  2095. static void
  2096. ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
  2097. {
  2098.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
  2099.         ar8327_set_mirror_regs(priv);
  2100.     } else {
  2101.         ar8216_set_mirror_regs(priv);
  2102.     }
  2103. }
  2104.  
  2105. static int
  2106. ar8xxx_sw_hw_apply(struct switch_dev *dev)
  2107. {
  2108.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2109.     u8 portmask[AR8X16_MAX_PORTS];
  2110.     int i, j;
  2111.  
  2112.     mutex_lock(&priv->reg_mutex);
  2113.     /* flush all vlan translation unit entries */
  2114.     priv->chip->vtu_flush(priv);
  2115.  
  2116.     memset(portmask, 0, sizeof(portmask));
  2117.     if (!priv->init) {
  2118.         /* calculate the port destination masks and load vlans
  2119.          * into the vlan translation unit */
  2120.         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  2121.             u8 vp = priv->vlan_table[j];
  2122.  
  2123.             if (!vp)
  2124.                 continue;
  2125.  
  2126.             for (i = 0; i < dev->ports; i++) {
  2127.                 u8 mask = BIT(i);
  2128.                 if (vp & mask)
  2129.                     portmask[i] |= vp & ~mask;
  2130.             }
  2131.             priv->chip->vtu_load_vlan(priv, j);
  2132.         }
  2133.     } else {
  2134.         /* vlan disabled:
  2135.          * isolate all ports, but connect them to the cpu port */
  2136.         for (i = 0; i < dev->ports; i++) {
  2137.             if (i == AR8216_PORT_CPU)
  2138.                 continue;
  2139.  
  2140.             portmask[i] = BIT(AR8216_PORT_CPU);
  2141.             portmask[AR8216_PORT_CPU] |= BIT(i);
  2142.         }
  2143.     }
  2144.  
  2145.     /* update the port destination mask registers and tag settings */
  2146.     for (i = 0; i < dev->ports; i++) {
  2147.         priv->chip->setup_port(priv, i, portmask[i]);
  2148.     }
  2149.  
  2150.     ar8xxx_set_mirror_regs(priv);
  2151.  
  2152.     mutex_unlock(&priv->reg_mutex);
  2153.     return 0;
  2154. }
  2155.  
  2156. static int
  2157. ar8xxx_sw_reset_switch(struct switch_dev *dev)
  2158. {
  2159.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2160.     int i;
  2161.  
  2162.     mutex_lock(&priv->reg_mutex);
  2163.     memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
  2164.         offsetof(struct ar8xxx_priv, vlan));
  2165.  
  2166.     for (i = 0; i < AR8X16_MAX_VLANS; i++)
  2167.         priv->vlan_id[i] = i;
  2168.  
  2169.     /* Configure all ports */
  2170.     for (i = 0; i < dev->ports; i++)
  2171.         priv->chip->init_port(priv, i);
  2172.  
  2173.     priv->mirror_rx = false;
  2174.     priv->mirror_tx = false;
  2175.     priv->source_port = 0;
  2176.     priv->monitor_port = 0;
  2177.  
  2178.     priv->chip->init_globals(priv);
  2179.  
  2180.     mutex_unlock(&priv->reg_mutex);
  2181.  
  2182.     return ar8xxx_sw_hw_apply(dev);
  2183. }
  2184.  
  2185. static int
  2186. ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
  2187.              const struct switch_attr *attr,
  2188.              struct switch_val *val)
  2189. {
  2190.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2191.     unsigned int len;
  2192.     int ret;
  2193.  
  2194.     if (!ar8xxx_has_mib_counters(priv))
  2195.         return -EOPNOTSUPP;
  2196.  
  2197.     mutex_lock(&priv->mib_lock);
  2198.  
  2199.     len = priv->dev.ports * priv->chip->num_mibs *
  2200.           sizeof(*priv->mib_stats);
  2201.     memset(priv->mib_stats, '\0', len);
  2202.     ret = ar8xxx_mib_flush(priv);
  2203.     if (ret)
  2204.         goto unlock;
  2205.  
  2206.     ret = 0;
  2207.  
  2208. unlock:
  2209.     mutex_unlock(&priv->mib_lock);
  2210.     return ret;
  2211. }
  2212.  
  2213. static int
  2214. ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
  2215.                    const struct switch_attr *attr,
  2216.                    struct switch_val *val)
  2217. {
  2218.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2219.  
  2220.     mutex_lock(&priv->reg_mutex);
  2221.     priv->mirror_rx = !!val->value.i;
  2222.     ar8xxx_set_mirror_regs(priv);
  2223.     mutex_unlock(&priv->reg_mutex);
  2224.  
  2225.     return 0;
  2226. }
  2227.  
  2228. static int
  2229. ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
  2230.                    const struct switch_attr *attr,
  2231.                    struct switch_val *val)
  2232. {
  2233.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2234.     val->value.i = priv->mirror_rx;
  2235.     return 0;
  2236. }
  2237.  
  2238. static int
  2239. ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
  2240.                    const struct switch_attr *attr,
  2241.                    struct switch_val *val)
  2242. {
  2243.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2244.  
  2245.     mutex_lock(&priv->reg_mutex);
  2246.     priv->mirror_tx = !!val->value.i;
  2247.     ar8xxx_set_mirror_regs(priv);
  2248.     mutex_unlock(&priv->reg_mutex);
  2249.  
  2250.     return 0;
  2251. }
  2252.  
  2253. static int
  2254. ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
  2255.                    const struct switch_attr *attr,
  2256.                    struct switch_val *val)
  2257. {
  2258.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2259.     val->value.i = priv->mirror_tx;
  2260.     return 0;
  2261. }
  2262.  
  2263. static int
  2264. ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
  2265.                   const struct switch_attr *attr,
  2266.                   struct switch_val *val)
  2267. {
  2268.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2269.  
  2270.     mutex_lock(&priv->reg_mutex);
  2271.     priv->monitor_port = val->value.i;
  2272.     ar8xxx_set_mirror_regs(priv);
  2273.     mutex_unlock(&priv->reg_mutex);
  2274.  
  2275.     return 0;
  2276. }
  2277.  
  2278. static int
  2279. ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
  2280.                   const struct switch_attr *attr,
  2281.                   struct switch_val *val)
  2282. {
  2283.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2284.     val->value.i = priv->monitor_port;
  2285.     return 0;
  2286. }
  2287.  
  2288. static int
  2289. ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
  2290.                  const struct switch_attr *attr,
  2291.                  struct switch_val *val)
  2292. {
  2293.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2294.  
  2295.     mutex_lock(&priv->reg_mutex);
  2296.     priv->source_port = val->value.i;
  2297.     ar8xxx_set_mirror_regs(priv);
  2298.     mutex_unlock(&priv->reg_mutex);
  2299.  
  2300.     return 0;
  2301. }
  2302.  
  2303. static int
  2304. ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
  2305.                  const struct switch_attr *attr,
  2306.                  struct switch_val *val)
  2307. {
  2308.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2309.     val->value.i = priv->source_port;
  2310.     return 0;
  2311. }
  2312.  
  2313. static int
  2314. ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
  2315.                  const struct switch_attr *attr,
  2316.                  struct switch_val *val)
  2317. {
  2318.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2319.     int port;
  2320.     int ret;
  2321.  
  2322.     if (!ar8xxx_has_mib_counters(priv))
  2323.         return -EOPNOTSUPP;
  2324.  
  2325.     port = val->port_vlan;
  2326.     if (port >= dev->ports)
  2327.         return -EINVAL;
  2328.  
  2329.     mutex_lock(&priv->mib_lock);
  2330.     ret = ar8xxx_mib_capture(priv);
  2331.     if (ret)
  2332.         goto unlock;
  2333.  
  2334.     ar8xxx_mib_fetch_port_stat(priv, port, true);
  2335.  
  2336.     ret = 0;
  2337.  
  2338. unlock:
  2339.     mutex_unlock(&priv->mib_lock);
  2340.     return ret;
  2341. }
  2342.  
  2343. static int
  2344. ar8xxx_sw_get_port_mib(struct switch_dev *dev,
  2345.                const struct switch_attr *attr,
  2346.                struct switch_val *val)
  2347. {
  2348.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  2349.     const struct ar8xxx_chip *chip = priv->chip;
  2350.     u64 *mib_stats;
  2351.     int port;
  2352.     int ret;
  2353.     char *buf = priv->buf;
  2354.     int i, len = 0;
  2355.  
  2356.     if (!ar8xxx_has_mib_counters(priv))
  2357.         return -EOPNOTSUPP;
  2358.  
  2359.     port = val->port_vlan;
  2360.     if (port >= dev->ports)
  2361.         return -EINVAL;
  2362.  
  2363.     mutex_lock(&priv->mib_lock);
  2364.     ret = ar8xxx_mib_capture(priv);
  2365.     if (ret)
  2366.         goto unlock;
  2367.  
  2368.     ar8xxx_mib_fetch_port_stat(priv, port, false);
  2369.  
  2370.     len += snprintf(buf + len, sizeof(priv->buf) - len,
  2371.             "Port %d MIB counters\n",
  2372.             port);
  2373.  
  2374.     mib_stats = &priv->mib_stats[port * chip->num_mibs];
  2375.     for (i = 0; i < chip->num_mibs; i++)
  2376.         len += snprintf(buf + len, sizeof(priv->buf) - len,
  2377.                 "%-12s: %llu\n",
  2378.                 chip->mib_decs[i].name,
  2379.                 mib_stats[i]);
  2380.  
  2381.     val->value.s = buf;
  2382.     val->len = len;
  2383.  
  2384.     ret = 0;
  2385.  
  2386. unlock:
  2387.     mutex_unlock(&priv->mib_lock);
  2388.     return ret;
  2389. }
  2390.  
  2391. static struct switch_attr ar8xxx_sw_attr_globals[] = {
  2392.     {
  2393.         .type = SWITCH_TYPE_INT,
  2394.         .name = "enable_vlan",
  2395.         .description = "Enable VLAN mode",
  2396.         .set = ar8xxx_sw_set_vlan,
  2397.         .get = ar8xxx_sw_get_vlan,
  2398.         .max = 1
  2399.     },
  2400.     {
  2401.         .type = SWITCH_TYPE_NOVAL,
  2402.         .name = "reset_mibs",
  2403.         .description = "Reset all MIB counters",
  2404.         .set = ar8xxx_sw_set_reset_mibs,
  2405.     },
  2406.     {
  2407.         .type = SWITCH_TYPE_INT,
  2408.         .name = "enable_mirror_rx",
  2409.         .description = "Enable mirroring of RX packets",
  2410.         .set = ar8xxx_sw_set_mirror_rx_enable,
  2411.         .get = ar8xxx_sw_get_mirror_rx_enable,
  2412.         .max = 1
  2413.     },
  2414.     {
  2415.         .type = SWITCH_TYPE_INT,
  2416.         .name = "enable_mirror_tx",
  2417.         .description = "Enable mirroring of TX packets",
  2418.         .set = ar8xxx_sw_set_mirror_tx_enable,
  2419.         .get = ar8xxx_sw_get_mirror_tx_enable,
  2420.         .max = 1
  2421.     },
  2422.     {
  2423.         .type = SWITCH_TYPE_INT,
  2424.         .name = "mirror_monitor_port",
  2425.         .description = "Mirror monitor port",
  2426.         .set = ar8xxx_sw_set_mirror_monitor_port,
  2427.         .get = ar8xxx_sw_get_mirror_monitor_port,
  2428.         .max = AR8216_NUM_PORTS - 1
  2429.     },
  2430.     {
  2431.         .type = SWITCH_TYPE_INT,
  2432.         .name = "mirror_source_port",
  2433.         .description = "Mirror source port",
  2434.         .set = ar8xxx_sw_set_mirror_source_port,
  2435.         .get = ar8xxx_sw_get_mirror_source_port,
  2436.         .max = AR8216_NUM_PORTS - 1
  2437.     },
  2438. };
  2439.  
  2440. static struct switch_attr ar8327_sw_attr_globals[] = {
  2441.     {
  2442.         .type = SWITCH_TYPE_INT,
  2443.         .name = "enable_vlan",
  2444.         .description = "Enable VLAN mode",
  2445.         .set = ar8xxx_sw_set_vlan,
  2446.         .get = ar8xxx_sw_get_vlan,
  2447.         .max = 1
  2448.     },
  2449.     {
  2450.         .type = SWITCH_TYPE_NOVAL,
  2451.         .name = "reset_mibs",
  2452.         .description = "Reset all MIB counters",
  2453.         .set = ar8xxx_sw_set_reset_mibs,
  2454.     },
  2455.     {
  2456.         .type = SWITCH_TYPE_INT,
  2457.         .name = "enable_mirror_rx",
  2458.         .description = "Enable mirroring of RX packets",
  2459.         .set = ar8xxx_sw_set_mirror_rx_enable,
  2460.         .get = ar8xxx_sw_get_mirror_rx_enable,
  2461.         .max = 1
  2462.     },
  2463.     {
  2464.         .type = SWITCH_TYPE_INT,
  2465.         .name = "enable_mirror_tx",
  2466.         .description = "Enable mirroring of TX packets",
  2467.         .set = ar8xxx_sw_set_mirror_tx_enable,
  2468.         .get = ar8xxx_sw_get_mirror_tx_enable,
  2469.         .max = 1
  2470.     },
  2471.     {
  2472.         .type = SWITCH_TYPE_INT,
  2473.         .name = "mirror_monitor_port",
  2474.         .description = "Mirror monitor port",
  2475.         .set = ar8xxx_sw_set_mirror_monitor_port,
  2476.         .get = ar8xxx_sw_get_mirror_monitor_port,
  2477.         .max = AR8327_NUM_PORTS - 1
  2478.     },
  2479.     {
  2480.         .type = SWITCH_TYPE_INT,
  2481.         .name = "mirror_source_port",
  2482.         .description = "Mirror source port",
  2483.         .set = ar8xxx_sw_set_mirror_source_port,
  2484.         .get = ar8xxx_sw_get_mirror_source_port,
  2485.         .max = AR8327_NUM_PORTS - 1
  2486.     },
  2487. };
  2488.  
  2489. static struct switch_attr ar8xxx_sw_attr_port[] = {
  2490.     {
  2491.         .type = SWITCH_TYPE_NOVAL,
  2492.         .name = "reset_mib",
  2493.         .description = "Reset single port MIB counters",
  2494.         .set = ar8xxx_sw_set_port_reset_mib,
  2495.     },
  2496.     {
  2497.         .type = SWITCH_TYPE_STRING,
  2498.         .name = "mib",
  2499.         .description = "Get port's MIB counters",
  2500.         .set = NULL,
  2501.         .get = ar8xxx_sw_get_port_mib,
  2502.     },
  2503. };
  2504.  
  2505. static struct switch_attr ar8xxx_sw_attr_vlan[] = {
  2506.     {
  2507.         .type = SWITCH_TYPE_INT,
  2508.         .name = "vid",
  2509.         .description = "VLAN ID (0-4094)",
  2510.         .set = ar8xxx_sw_set_vid,
  2511.         .get = ar8xxx_sw_get_vid,
  2512.         .max = 4094,
  2513.     },
  2514. };
  2515.  
  2516. static const struct switch_dev_ops ar8xxx_sw_ops = {
  2517.     .attr_global = {
  2518.         .attr = ar8xxx_sw_attr_globals,
  2519.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
  2520.     },
  2521.     .attr_port = {
  2522.         .attr = ar8xxx_sw_attr_port,
  2523.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  2524.     },
  2525.     .attr_vlan = {
  2526.         .attr = ar8xxx_sw_attr_vlan,
  2527.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  2528.     },
  2529.     .get_port_pvid = ar8xxx_sw_get_pvid,
  2530.     .set_port_pvid = ar8xxx_sw_set_pvid,
  2531.     .get_vlan_ports = ar8216_sw_get_ports,
  2532.     .set_vlan_ports = ar8216_sw_set_ports,
  2533.     .apply_config = ar8xxx_sw_hw_apply,
  2534.     .reset_switch = ar8xxx_sw_reset_switch,
  2535.     .get_port_link = ar8xxx_sw_get_port_link,
  2536. };
  2537.  
  2538. static const struct switch_dev_ops ar8327_sw_ops = {
  2539.     .attr_global = {
  2540.         .attr = ar8327_sw_attr_globals,
  2541.         .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
  2542.     },
  2543.     .attr_port = {
  2544.         .attr = ar8xxx_sw_attr_port,
  2545.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  2546.     },
  2547.     .attr_vlan = {
  2548.         .attr = ar8xxx_sw_attr_vlan,
  2549.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  2550.     },
  2551.     .get_port_pvid = ar8xxx_sw_get_pvid,
  2552.     .set_port_pvid = ar8xxx_sw_set_pvid,
  2553.     .get_vlan_ports = ar8327_sw_get_ports,
  2554.     .set_vlan_ports = ar8327_sw_set_ports,
  2555.     .apply_config = ar8xxx_sw_hw_apply,
  2556.     .reset_switch = ar8xxx_sw_reset_switch,
  2557.     .get_port_link = ar8xxx_sw_get_port_link,
  2558. };
  2559.  
  2560. static int
  2561. ar8xxx_id_chip(struct ar8xxx_priv *priv)
  2562. {
  2563.     u32 val;
  2564.     u16 id;
  2565.     int i;
  2566.  
  2567.     val = priv->read(priv, AR8216_REG_CTRL);
  2568.     if (val == ~0)
  2569.         return -ENODEV;
  2570.  
  2571.     id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  2572.     for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
  2573.         u16 t;
  2574.  
  2575.         val = priv->read(priv, AR8216_REG_CTRL);
  2576.         if (val == ~0)
  2577.             return -ENODEV;
  2578.  
  2579.         t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  2580.         if (t != id)
  2581.             return -ENODEV;
  2582.     }
  2583.  
  2584.     priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
  2585.     priv->chip_rev = (id & AR8216_CTRL_REVISION);
  2586.  
  2587.     switch (priv->chip_ver) {
  2588.     case AR8XXX_VER_AR8216:
  2589.         priv->chip = &ar8216_chip;
  2590.         break;
  2591.     case AR8XXX_VER_AR8236:
  2592.         priv->chip = &ar8236_chip;
  2593.         break;
  2594.     case AR8XXX_VER_AR8316:
  2595.         priv->chip = &ar8316_chip;
  2596.         break;
  2597.     case AR8XXX_VER_AR8327:
  2598.         priv->mii_lo_first = true;
  2599.         priv->chip = &ar8327_chip;
  2600.         break;
  2601.     case AR8XXX_VER_AR8337:
  2602.         priv->mii_lo_first = true;
  2603.         priv->chip = &ar8327_chip;
  2604.         break;
  2605.     default:
  2606.         pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
  2607.                priv->chip_ver, priv->chip_rev);
  2608.  
  2609.         return -ENODEV;
  2610.     }
  2611.  
  2612.     return 0;
  2613. }
  2614.  
  2615. static void
  2616. ar8xxx_mib_work_func(struct work_struct *work)
  2617. {
  2618.     struct ar8xxx_priv *priv;
  2619.     int err;
  2620.  
  2621.     priv = container_of(work, struct ar8xxx_priv, mib_work.work);
  2622.  
  2623.     mutex_lock(&priv->mib_lock);
  2624.  
  2625.     err = ar8xxx_mib_capture(priv);
  2626.     if (err)
  2627.         goto next_port;
  2628.  
  2629.     ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
  2630.  
  2631. next_port:
  2632.     priv->mib_next_port++;
  2633.     if (priv->mib_next_port >= priv->dev.ports)
  2634.         priv->mib_next_port = 0;
  2635.  
  2636.     mutex_unlock(&priv->mib_lock);
  2637.     schedule_delayed_work(&priv->mib_work,
  2638.                   msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  2639. }
  2640.  
  2641. static int
  2642. ar8xxx_mib_init(struct ar8xxx_priv *priv)
  2643. {
  2644.     unsigned int len;
  2645.  
  2646.     if (!ar8xxx_has_mib_counters(priv))
  2647.         return 0;
  2648.  
  2649.     BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
  2650.  
  2651.     len = priv->dev.ports * priv->chip->num_mibs *
  2652.           sizeof(*priv->mib_stats);
  2653.     priv->mib_stats = kzalloc(len, GFP_KERNEL);
  2654.  
  2655.     if (!priv->mib_stats)
  2656.         return -ENOMEM;
  2657.  
  2658.     return 0;
  2659. }
  2660.  
  2661. static void
  2662. ar8xxx_mib_start(struct ar8xxx_priv *priv)
  2663. {
  2664.     if (!ar8xxx_has_mib_counters(priv))
  2665.         return;
  2666.  
  2667.     schedule_delayed_work(&priv->mib_work,
  2668.                   msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  2669. }
  2670.  
  2671. static void
  2672. ar8xxx_mib_stop(struct ar8xxx_priv *priv)
  2673. {
  2674.     if (!ar8xxx_has_mib_counters(priv))
  2675.         return;
  2676.  
  2677.     cancel_delayed_work(&priv->mib_work);
  2678. }
  2679.  
  2680. static struct ar8xxx_priv *
  2681. ar8xxx_create(void)
  2682. {
  2683.     struct ar8xxx_priv *priv;
  2684.  
  2685.     priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
  2686.     if (priv == NULL)
  2687.         return NULL;
  2688.  
  2689.     mutex_init(&priv->reg_mutex);
  2690.     mutex_init(&priv->mib_lock);
  2691.     INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
  2692.  
  2693.     return priv;
  2694. }
  2695.  
  2696. static void
  2697. ar8xxx_free(struct ar8xxx_priv *priv)
  2698. {
  2699.     if (priv->chip && priv->chip->cleanup)
  2700.         priv->chip->cleanup(priv);
  2701.  
  2702.     kfree(priv->mib_stats);
  2703.     kfree(priv);
  2704. }
  2705.  
  2706. static struct ar8xxx_priv *
  2707. ar8xxx_create_mii(struct mii_bus *bus)
  2708. {
  2709.     struct ar8xxx_priv *priv;
  2710.  
  2711.     priv = ar8xxx_create();
  2712.     if (priv) {
  2713.         priv->mii_bus = bus;
  2714.         priv->read = ar8xxx_mii_read;
  2715.         priv->write = ar8xxx_mii_write;
  2716.         priv->rmw = ar8xxx_mii_rmw;
  2717.     }
  2718.  
  2719.     return priv;
  2720. }
  2721.  
  2722. static int
  2723. ar8xxx_probe_switch(struct ar8xxx_priv *priv)
  2724. {
  2725.     struct switch_dev *swdev;
  2726.     int ret;
  2727.  
  2728.     ret = ar8xxx_id_chip(priv);
  2729.     if (ret)
  2730.         return ret;
  2731.  
  2732.     swdev = &priv->dev;
  2733.     swdev->cpu_port = AR8216_PORT_CPU;
  2734.     swdev->ops = &ar8xxx_sw_ops;
  2735.  
  2736.     if (chip_is_ar8316(priv)) {
  2737.         swdev->name = "Atheros AR8316";
  2738.         swdev->vlans = AR8X16_MAX_VLANS;
  2739.         swdev->ports = AR8216_NUM_PORTS;
  2740.     } else if (chip_is_ar8236(priv)) {
  2741.         swdev->name = "Atheros AR8236";
  2742.         swdev->vlans = AR8216_NUM_VLANS;
  2743.         swdev->ports = AR8216_NUM_PORTS;
  2744.     } else if (chip_is_ar8327(priv)) {
  2745.         swdev->name = "Atheros AR8327";
  2746.         swdev->vlans = AR8X16_MAX_VLANS;
  2747.         swdev->ports = AR8327_NUM_PORTS;
  2748.         swdev->ops = &ar8327_sw_ops;
  2749.     } else if (chip_is_ar8337(priv)) {
  2750.         swdev->name = "Atheros AR8337";
  2751.         swdev->vlans = AR8X16_MAX_VLANS;
  2752.         swdev->ports = AR8327_NUM_PORTS;
  2753.         swdev->ops = &ar8327_sw_ops;
  2754.     } else {
  2755.         swdev->name = "Atheros AR8216";
  2756.         swdev->vlans = AR8216_NUM_VLANS;
  2757.         swdev->ports = AR8216_NUM_PORTS;
  2758.     }
  2759.  
  2760.     ret = ar8xxx_mib_init(priv);
  2761.     if (ret)
  2762.         return ret;
  2763.  
  2764.     return 0;
  2765. }
  2766.  
  2767. static int
  2768. ar8xxx_start(struct ar8xxx_priv *priv)
  2769. {
  2770.     int ret;
  2771.  
  2772.     priv->init = true;
  2773.  
  2774.     ret = priv->chip->hw_init(priv);
  2775.     if (ret)
  2776.         return ret;
  2777.  
  2778.     ret = ar8xxx_sw_reset_switch(&priv->dev);
  2779.     if (ret)
  2780.         return ret;
  2781.  
  2782.     priv->init = false;
  2783.  
  2784.     ar8xxx_mib_start(priv);
  2785.  
  2786.     return 0;
  2787. }
  2788.  
  2789. static int
  2790. ar8xxx_phy_config_init(struct phy_device *phydev)
  2791. {
  2792.     struct ar8xxx_priv *priv = phydev->priv;
  2793.     struct net_device *dev = phydev->attached_dev;
  2794.     int ret;
  2795.  
  2796.     if (WARN_ON(!priv))
  2797.         return -ENODEV;
  2798.  
  2799.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  2800.         return 0;
  2801.  
  2802.     priv->phy = phydev;
  2803.  
  2804.     if (phydev->addr != 0) {
  2805.         if (chip_is_ar8316(priv)) {
  2806.             /* switch device has been initialized, reinit */
  2807.             priv->dev.ports = (AR8216_NUM_PORTS - 1);
  2808.             priv->initialized = false;
  2809.             priv->port4_phy = true;
  2810.             ar8316_hw_init(priv);
  2811.             return 0;
  2812.         }
  2813.  
  2814.         return 0;
  2815.     }
  2816.  
  2817.     ret = ar8xxx_start(priv);
  2818.     if (ret)
  2819.         return ret;
  2820.  
  2821.     /* VID fixup only needed on ar8216 */
  2822.     if (chip_is_ar8216(priv)) {
  2823.         dev->phy_ptr = priv;
  2824.         dev->priv_flags |= IFF_NO_IP_ALIGN;
  2825.         dev->eth_mangle_rx = ar8216_mangle_rx;
  2826.         dev->eth_mangle_tx = ar8216_mangle_tx;
  2827.     }
  2828.  
  2829.     return 0;
  2830. }
  2831.  
  2832. static int
  2833. ar8xxx_phy_read_status(struct phy_device *phydev)
  2834. {
  2835.     struct ar8xxx_priv *priv = phydev->priv;
  2836.     struct switch_port_link link;
  2837.     int ret;
  2838.  
  2839.     if (phydev->addr != 0)
  2840.         return genphy_read_status(phydev);
  2841.  
  2842.     ar8216_read_port_link(priv, phydev->addr, &link);
  2843.     phydev->link = !!link.link;
  2844.     if (!phydev->link)
  2845.         return 0;
  2846.  
  2847.     switch (link.speed) {
  2848.     case SWITCH_PORT_SPEED_10:
  2849.         phydev->speed = SPEED_10;
  2850.         break;
  2851.     case SWITCH_PORT_SPEED_100:
  2852.         phydev->speed = SPEED_100;
  2853.         break;
  2854.     case SWITCH_PORT_SPEED_1000:
  2855.         phydev->speed = SPEED_1000;
  2856.         break;
  2857.     default:
  2858.         phydev->speed = 0;
  2859.     }
  2860.     phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
  2861.  
  2862.     /* flush the address translation unit */
  2863.     mutex_lock(&priv->reg_mutex);
  2864.     ret = priv->chip->atu_flush(priv);
  2865.     mutex_unlock(&priv->reg_mutex);
  2866.  
  2867.     phydev->state = PHY_RUNNING;
  2868.     netif_carrier_on(phydev->attached_dev);
  2869.     phydev->adjust_link(phydev->attached_dev);
  2870.  
  2871.     return ret;
  2872. }
  2873.  
  2874. static int
  2875. ar8xxx_phy_config_aneg(struct phy_device *phydev)
  2876. {
  2877.     if (phydev->addr == 0)
  2878.         return 0;
  2879.  
  2880.     return genphy_config_aneg(phydev);
  2881. }
  2882.  
  2883. static const u32 ar8xxx_phy_ids[] = {
  2884.     0x004dd033,
  2885.     0x004dd034, /* AR8327 */
  2886.     0x004dd036, /* AR8337 */
  2887.     0x004dd041,
  2888.     0x004dd042,
  2889. };
  2890.  
  2891. static bool
  2892. ar8xxx_phy_match(u32 phy_id)
  2893. {
  2894.     int i;
  2895.  
  2896.     for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
  2897.         if (phy_id == ar8xxx_phy_ids[i])
  2898.             return true;
  2899.  
  2900.     return false;
  2901. }
  2902.  
  2903. static bool
  2904. ar8xxx_is_possible(struct mii_bus *bus)
  2905. {
  2906.     unsigned i;
  2907.  
  2908.     for (i = 0; i < 4; i++) {
  2909.         u32 phy_id;
  2910.  
  2911.         phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
  2912.         phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
  2913.         if (!ar8xxx_phy_match(phy_id)) {
  2914.             pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
  2915.                  dev_name(&bus->dev), i, phy_id);
  2916.             return false;
  2917.         }
  2918.     }
  2919.  
  2920.     return true;
  2921. }
  2922.  
  2923. static int
  2924. ar8xxx_phy_probe(struct phy_device *phydev)
  2925. {
  2926.     struct ar8xxx_priv *priv;
  2927.     struct switch_dev *swdev;
  2928.     int ret;
  2929.  
  2930.     /* skip PHYs at unused adresses */
  2931.     if (phydev->addr != 0 && phydev->addr != 4)
  2932.         return -ENODEV;
  2933.  
  2934.     if (!ar8xxx_is_possible(phydev->bus))
  2935.         return -ENODEV;
  2936.  
  2937.     mutex_lock(&ar8xxx_dev_list_lock);
  2938.     list_for_each_entry(priv, &ar8xxx_dev_list, list)
  2939.         if (priv->mii_bus == phydev->bus)
  2940.             goto found;
  2941.  
  2942.     priv = ar8xxx_create_mii(phydev->bus);
  2943.     if (priv == NULL) {
  2944.         ret = -ENOMEM;
  2945.         goto unlock;
  2946.     }
  2947.  
  2948.     ret = ar8xxx_probe_switch(priv);
  2949.     if (ret)
  2950.         goto free_priv;
  2951.  
  2952.     swdev = &priv->dev;
  2953.     swdev->alias = dev_name(&priv->mii_bus->dev);
  2954.     ret = register_switch(swdev, NULL);
  2955.     if (ret)
  2956.         goto free_priv;
  2957.  
  2958.     pr_info("%s: %s rev. %u switch registered on %s\n",
  2959.         swdev->devname, swdev->name, priv->chip_rev,
  2960.         dev_name(&priv->mii_bus->dev));
  2961.  
  2962. found:
  2963.     priv->use_count++;
  2964.  
  2965.     if (phydev->addr == 0) {
  2966.         if (ar8xxx_has_gige(priv)) {
  2967.             phydev->supported = SUPPORTED_1000baseT_Full;
  2968.             phydev->advertising = ADVERTISED_1000baseT_Full;
  2969.         } else {
  2970.             phydev->supported = SUPPORTED_100baseT_Full;
  2971.             phydev->advertising = ADVERTISED_100baseT_Full;
  2972.         }
  2973.  
  2974.         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
  2975.             priv->phy = phydev;
  2976.  
  2977.             ret = ar8xxx_start(priv);
  2978.             if (ret)
  2979.                 goto err_unregister_switch;
  2980.         }
  2981.     } else {
  2982.         if (ar8xxx_has_gige(priv)) {
  2983.             phydev->supported |= SUPPORTED_1000baseT_Full;
  2984.             phydev->advertising |= ADVERTISED_1000baseT_Full;
  2985.         }
  2986.     }
  2987.  
  2988.     phydev->priv = priv;
  2989.  
  2990.     list_add(&priv->list, &ar8xxx_dev_list);
  2991.  
  2992.     mutex_unlock(&ar8xxx_dev_list_lock);
  2993.  
  2994.     return 0;
  2995.  
  2996. err_unregister_switch:
  2997.     if (--priv->use_count)
  2998.         goto unlock;
  2999.  
  3000.     unregister_switch(&priv->dev);
  3001.  
  3002. free_priv:
  3003.     ar8xxx_free(priv);
  3004. unlock:
  3005.     mutex_unlock(&ar8xxx_dev_list_lock);
  3006.     return ret;
  3007. }
  3008.  
  3009. static void
  3010. ar8xxx_phy_detach(struct phy_device *phydev)
  3011. {
  3012.     struct net_device *dev = phydev->attached_dev;
  3013.  
  3014.     if (!dev)
  3015.         return;
  3016.  
  3017.     dev->phy_ptr = NULL;
  3018.     dev->priv_flags &= ~IFF_NO_IP_ALIGN;
  3019.     dev->eth_mangle_rx = NULL;
  3020.     dev->eth_mangle_tx = NULL;
  3021. }
  3022.  
  3023. static void
  3024. ar8xxx_phy_remove(struct phy_device *phydev)
  3025. {
  3026.     struct ar8xxx_priv *priv = phydev->priv;
  3027.  
  3028.     if (WARN_ON(!priv))
  3029.         return;
  3030.  
  3031.     phydev->priv = NULL;
  3032.     if (--priv->use_count > 0)
  3033.         return;
  3034.  
  3035.     mutex_lock(&ar8xxx_dev_list_lock);
  3036.     list_del(&priv->list);
  3037.     mutex_unlock(&ar8xxx_dev_list_lock);
  3038.  
  3039.     unregister_switch(&priv->dev);
  3040.     ar8xxx_mib_stop(priv);
  3041.     ar8xxx_free(priv);
  3042. }
  3043.  
  3044. static struct phy_driver ar8xxx_phy_driver = {
  3045.     .phy_id     = 0x004d0000,
  3046.     .name       = "Atheros AR8216/AR8236/AR8316",
  3047.     .phy_id_mask    = 0xffff0000,
  3048.     .features   = PHY_BASIC_FEATURES,
  3049.     .probe      = ar8xxx_phy_probe,
  3050.     .remove     = ar8xxx_phy_remove,
  3051.     .detach     = ar8xxx_phy_detach,
  3052.     .config_init    = ar8xxx_phy_config_init,
  3053.     .config_aneg    = ar8xxx_phy_config_aneg,
  3054.     .read_status    = ar8xxx_phy_read_status,
  3055.     .driver     = { .owner = THIS_MODULE },
  3056. };
  3057.  
  3058. int __init
  3059. ar8xxx_init(void)
  3060. {
  3061.     return phy_driver_register(&ar8xxx_phy_driver);
  3062. }
  3063.  
  3064. void __exit
  3065. ar8xxx_exit(void)
  3066. {
  3067.     phy_driver_unregister(&ar8xxx_phy_driver);
  3068. }
  3069.  
  3070. module_init(ar8xxx_init);
  3071. module_exit(ar8xxx_exit);
  3072. MODULE_LICENSE("GPL");
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