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- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- * UNHANDLED CASE: READ REGISTER 50..55 with INDIRECT_REGISTER $00 and OFFSET $00 *
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
- * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- Repeated for channel B
- Repeated 2 times
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- - CLOCK BIT: 00
- * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
- * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
- * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 02 <- 10 Interrupt vector
- * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
- * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
- * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- Repeated for channel B
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- (RECOMPUTE) FREQUENCY: 600f to COMM.CONTROL REGISTER
- * :upd7201:chbB 04 <- 10 x32 Clock, Synchronous mode
- * :upd7201:chbB 01 <- 18 Interrupt + DMA on received character
- * :upd7201:chbB 02 <- 00 No DMA
- * :upd7201:chbB 03 <- c0 Receiver disabled, 8 bit
- * :upd7201:chbB 05 <- 00 Transmitter disabled
- * :upd7201:chbB 06 <- cf Sync byte 1
- * :upd7201:chbB 07 <- f3 Sync byte 2
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
- * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- Repeated for Channel B
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- - CLOCK BIT: 00
- * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
- * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
- * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 02 <- 10 Interrupt vector
- * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
- * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
- * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
- Repeated for channel B
- Repeated 3 times
- **** COMM HANDLER INSTALLED ****
- * :upd7201:chbB 00 <- 18
- * :upd7201:chaA 00 <- 18
- **** COMM HANDLER INSTALLED ****
- * :upd7201:chbB 00 <- 18
- * :upd7201:chaA 00 <- 18
- **** COMM HANDLER INSTALLED ****
- * :upd7201:chbB 00 <- 18
- * :upd7201:chaA 00 <- 18
- (RECOMPUTE) * INTERLACED *
- (RECOMPUTE) * LINEDOUBLER *
- (RECOMPUTE) FREQUENCY: 60
- * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
- * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
- * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
- - CLOCK BIT: 00
- * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
- * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
- * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 02 <- 10 Interrupt vector
- * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
- * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- - CLOCK BIT: 00
- * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
- * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
- * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chbB 01 <- 15 Interrupt on received character, Ext Status, status affect vector
- * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
- * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
- * :upd7201:chaA 02 <- 10 Interrupt vector
- * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
- * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
- * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
- * :upd7201:chaA 01 <- 10 Interrupt on received character
- ff to COMM.CONTROL REGISTER
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
- * :upd7201:chaA 00 <- 01
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