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Jul 29th, 2015
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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 19:35:38 07/29/2015
  6. -- Design Name:
  7. -- Module Name: sevensega - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity sevensega is
  33. Port ( i0 : in STD_LOGIC;
  34. i1 : in STD_LOGIC;
  35. i2 : in STD_LOGIC;
  36. a : out STD_LOGIC;
  37. b : out STD_LOGIC;
  38. c : out STD_LOGIC;
  39. d : out STD_LOGIC;
  40. e : out STD_LOGIC;
  41. f : out STD_LOGIC;
  42. g : out STD_LOGIC);
  43. end sevensega;
  44.  
  45. architecture Behavioral of sevensega is
  46.  
  47. begin
  48. a <= (not i1) and ((not i2 and i0) or (i2 and not i0));
  49. b <= i2 and ((not i1 and i0) or (i1 and not i0));
  50. c <= (not i2) and i1 and (not i0);
  51. d <= (not i2 and not i1 and not i0) or (i2 and not i1 and not i0) or (i2 and i1 and i0);
  52. e <= (not i2 and i0) or (i2 and not i1) or (i2 and i1 and i0);
  53. f <= (not i2 and not i1 and i0) or (not i2 and i1 and not i0) or (not i2 and i1 and i0) or (i2 and i1 and i0);
  54. g <= (not i2 and not i1) or (i2 and i1 and i0);
  55.  
  56. end Behavioral;
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