Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 19:35:38 07/29/2015
- -- Design Name:
- -- Module Name: sevensega - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity sevensega is
- Port ( i0 : in STD_LOGIC;
- i1 : in STD_LOGIC;
- i2 : in STD_LOGIC;
- a : out STD_LOGIC;
- b : out STD_LOGIC;
- c : out STD_LOGIC;
- d : out STD_LOGIC;
- e : out STD_LOGIC;
- f : out STD_LOGIC;
- g : out STD_LOGIC);
- end sevensega;
- architecture Behavioral of sevensega is
- begin
- a <= (not i1) and ((not i2 and i0) or (i2 and not i0));
- b <= i2 and ((not i1 and i0) or (i1 and not i0));
- c <= (not i2) and i1 and (not i0);
- d <= (not i2 and not i1 and not i0) or (i2 and not i1 and not i0) or (i2 and i1 and i0);
- e <= (not i2 and i0) or (i2 and not i1) or (i2 and i1 and i0);
- f <= (not i2 and not i1 and i0) or (not i2 and i1 and not i0) or (not i2 and i1 and i0) or (i2 and i1 and i0);
- g <= (not i2 and not i1) or (i2 and i1 and i0);
- end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement